Patents by Inventor Tomoaki Daigi

Tomoaki Daigi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8441527
    Abstract: A 3D image processing apparatus includes: a main screen image processing unit which generates a main screen processed image by performing a format conversion process on a main screen image; a sub screen image processing unit which generates a sub screen processed image by performing a format conversion process on a sub screen image; and a synthesizing unit which generates a synthesized image by synthesizing the main screen processed image and the sub screen processed image. Furthermore, the main screen image processing unit generates a left screen output image by performing the format conversion process on a left screen input image that is a left half of a 3D image, and the sub screen image processing unit generates a right screen output image by performing the format conversion process on a right screen input image that is a right half of a 3D image.
    Type: Grant
    Filed: August 3, 2011
    Date of Patent: May 14, 2013
    Assignee: Panasonic Corporation
    Inventor: Tomoaki Daigi
  • Publication number: 20110285706
    Abstract: A 3D image processing apparatus includes: a main screen image processing unit which generates a main screen processed image by performing a format conversion process on a main screen image; a sub screen image processing unit which generates a sub screen processed image by performing a format conversion process on a sub screen image; and a synthesizing unit which generates a synthesized image by synthesizing the main screen processed image and the sub screen processed image. Furthermore, the main screen image processing unit generates a left screen output image by performing the format conversion process on a left screen input image that is a left half of a 3D image, and the sub screen image processing unit generates a right screen output image by performing the format conversion process on a right screen input image that is a right half of a 3D image.
    Type: Application
    Filed: August 3, 2011
    Publication date: November 24, 2011
    Applicant: PANASONIC CORPORATION
    Inventor: Tomoaki DAIGI
  • Patent number: 7474354
    Abstract: A binarizer binarizes a video signal input from an A/D converter and a video signal output from a line memory using an average luminance value provided from a detection window video signal processor as a threshold value, and outputs a binary pattern. A reference pattern generator generates a plurality of reference patterns. An angle detector compares the binary pattern with each of the plurality of reference patterns, and outputs the angle of a matched reference pattern as angle information. An arc shape detector outputs the edge angle information of a picture based on a combination of the angle information of an interpolation scanning line including an object interpolation pixel and the angle information of interpolation scanning lines above and below the interpolation scanning line.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: January 6, 2009
    Assignee: Panasonic Corporation
    Inventors: Hideaki Kawamura, Mitsuhiro Kasahara, Tomoaki Daigi
  • Patent number: 7446815
    Abstract: A first video signal generation circuit newly generates pixels between pixels in a first progressive video field signal outputted by a first progressive video generation circuit, and outputs a third progressive video field signal. A second video signal generation circuit newly generates pixels between pixels in a second progressive video field signal outputted by a second progressive video generation circuit, and outputs a fourth progressive video field signal. A comparison circuit compares the third progressive video field signal and the fourth progressive video field signal, and outputs the result of the comparison as motion amount information. An output circuit synthesizes an intra-field interpolation signal and a frame interfiled interpolation signal on the basis of the motion amount information, and outputs a composite signal as a progressive video signal.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: November 4, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuhiro Kasahara, Tomoaki Daigi, Hideaki Kawamura, Hideto Nakahigashi, Tomoko Morita
  • Patent number: 7388617
    Abstract: A plurality of interlaced video signals respectively corresponding to a plurality of continuous fields are generated by first, second, and third one-field delay circuits on the basis of an inputted interlaced video signal. A first progressive video field signal is generated by a first progressive video generation circuit on the basis of the plurality of interlaced video signals. A second progressive video field signal is generated by a second progressive video generation circuit on the basis of the plurality of interlaced video signals. Motion amount information in the vertical direction of a picture is calculated by a comparison circuit on the basis of the first progressive video field signal and the second progressive video field signal.
    Type: Grant
    Filed: April 14, 2003
    Date of Patent: June 17, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuhiro Kasahara, Tomoaki Daigi, Hideaki Kawamura, Hideto Nakahigashi, Tomoko Morita
  • Patent number: 7116842
    Abstract: An image processing method and apparatus for converting an original image by performing a pixel number conversion on the original image at a predetermined pixel number conversion rate in at least one of a column direction and a row direction in a matrix that has been specified. A character judging step determines whether each of a plurality of areas making up the original image is a character part or not. When it is determined that image has a character part, a pixel number conversion procedure is performed so that the lines within the original image are converted into lines with the same line width in the converted image. Alternatively, areas that are judged a character part can use an alternative pixel number conversion procedure so that a barycenter in the original image is maintained after the pixel number conversion.
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: October 3, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Tomoaki Daigi
  • Publication number: 20060187348
    Abstract: A synchronization signal generating apparatus comprises a cycle setting section, a pulse masking section, and a pulse generating section. The pulse masking section outputs a pulse train based on an input pulse train and cycle information. The pulse generating section outputs a pulse train based on the pulse train and cycle information output from the pulse masking section. When a synchronization signal is switched from the state of being in synchronization with the pulse train input from the pulse masking section to the independent state, the cycle setting section switches the cycle information upon receiving a pulse of the pulse train for the first time since a cycle selection signal was changed.
    Type: Application
    Filed: February 9, 2006
    Publication date: August 24, 2006
    Inventors: Tomoaki Daigi, Yoichiro Miki
  • Patent number: 6999128
    Abstract: An inter-frame motion detector detects the presence or absence of motion between frames on the basis of judgment whether or not an inter-frame difference is not more than a set value. A vertical edge continuity detector calculates difference values between an object pixel and pixels above or below the object pixel in an inlaid picture, and detects whether or not there is horizontal continuity of an inter-field vertical edge on the basis of judgment whether or not the signs of the difference values are the same continuously over not less than a predetermined number of pixels, in the horizontal direction, including the object pixel. When it is detected that there is no motion between frames, and it is detected that there is horizontal continuity of the inter-field vertical edge, it is judged that a picture is in a completely still state.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: February 14, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Mitsuhiro Kasahara, Tomoaki Daigi, Hideaki Kawamura
  • Patent number: 6924844
    Abstract: A binarizer binarizes a video signal VD1 inputted from an A/D converter and a video signal VD2 outputted from a line memory using an average luminance value LU fed from a detection window video signal processor as a threshold value, to output a binary pattern BI. A reference pattern generator generates a plurality of reference patterns RA. A first pattern matching angle detector compares the binary pattern BI with each of the plurality of reference patterns RA, to output the angle of the reference pattern RA which matches with the binary pattern BI as angle information PA. A detected isolation point remover 4 outputs angle signal AN when the angle information PA has continuity.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: August 2, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Kawamura, Mitsuhiro Kasahara, Tomoaki Daigi
  • Publication number: 20050151878
    Abstract: A plurality of interlaced video signals respectively corresponding to a plurality of continuous fields are generated by first, second, and third one-field delay circuits on the basis of an inputted interlaced video signal. A first progressive video field signal is generated by a first progressive video generation circuit on the basis of the plurality of interlaced video signals. A second progressive video field signal is generated by a second progressive video generation circuit on the basis of the plurality of interlaced video signals. Motion amount information in the vertical direction of a picture is calculated by a comparison circuit on the basis of the first progressive video field signal and the second progressive video field signal.
    Type: Application
    Filed: April 14, 2003
    Publication date: July 14, 2005
    Inventors: Mitsuhiro Kasahara, Tomoaki Daigi, Hideaki Kawamura, Hideto Nakahigashi, Tomoko Morita
  • Publication number: 20050140664
    Abstract: A binarizer binarizes a video signal input from an A/D converter and a video signal output from a line memory using an average luminance value provided from a detection window video signal processor as a threshold value, and outputs a binary pattern. A reference pattern generater generates a plurality of reference patterns. An angle detector compares the binary pattern with each of the plurality of reference patterns, and outputs the angle of a matched reference pattern as angle information. An arc shape detector outputs the edge angle information of a picture based on a combination of the angle information of an interpolation scanning line including an object interpolation pixel and the angle information of interpolation scanning lines above and below the interpolation scanning line.
    Type: Application
    Filed: April 30, 2003
    Publication date: June 30, 2005
    Inventors: Hideaki Kawamura, Mitsuhiro Kasahara, Tomoaki Daigi
  • Publication number: 20050140825
    Abstract: A first video signal generation circuit newly generates pixels between pixels in a first progressive video field signal outputted by a first progressive video generation circuit, and outputs a third progressive video field signal. A second video signal generation circuit newly generates pixels between pixels in a second progressive video field signal outputted by a second progressive video generation circuit, and outputs a fourth progressive video field signal. A comparison circuit compares the third progressive video field signal and the fourth progressive video field signal, and outputs the result of the comparison as motion amount information. An output circuit synthesizes an intra-field interpolation signal and a frame interfiled interpolation signal on the basis of the motion amount information, and outputs a composite signal as a progressive video signal.
    Type: Application
    Filed: April 14, 2003
    Publication date: June 30, 2005
    Inventors: Mitsuhiro Kasahara, Tomoaki Daigi, Hideaki Kawamura, Hideto Nakahigashi, Tomoko Morita
  • Patent number: 6801221
    Abstract: A vertical interpolation circuit interpolates an interpolated pixel with pixels located on upper and lower vertical positions, and outputs a vertical interpolated value. An oblique averaging part averages pixels obliquely located with respect to the interpolated pixel on the basis of an oblique edge angle signal, and outputs the result of calculation as an oblique average. An oblique difference absolute value operation part calculates the absolute value of the difference between the values of the pixels obliquely located with respect to the interpolated pixel on the basis of the oblique edge angle signal, and outputs the result of calculation as an oblique difference absolute value. A mixing part outputs the vertical interpolated value, the oblique average or a mixed value thereof as an interpolated pixel value on the basis of the oblique difference absolute value.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: October 5, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Kawamura, Mitsuhiro Kasahara, Tomoaki Daigi
  • Publication number: 20030099410
    Abstract: The object of the present invention is to provide an image processing method and an image processing apparatus for obtaining an image of a good quality without blurriness, which does not look strange to viewers.
    Type: Application
    Filed: October 18, 2002
    Publication date: May 29, 2003
    Inventor: Tomoaki Daigi
  • Publication number: 20030038817
    Abstract: A vertical interpolation circuit interpolates an interpolated pixel with pixels located on upper and lower vertical positions, and outputs a vertical interpolated value. An oblique averaging part averages pixels obliquely located with respect to the interpolated pixel on the basis of an oblique edge angle signal, and outputs the result of calculation as an oblique average. An oblique difference absolute value operation part calculates the absolute value of the difference between the values of the pixels obliquely located with respect to the interpolated pixel on the basis of the oblique edge angle signal, and outputs the result of calculation as an oblique difference absolute value. A mixing part outputs the vertical interpolated value, the oblique average or a mixed value thereof as an interpolated pixel value on the basis of the oblique difference absolute value.
    Type: Application
    Filed: July 18, 2002
    Publication date: February 27, 2003
    Inventors: Hideaki Kawamura, Mitsuhiro Kasahara, Tomoaki Daigi
  • Publication number: 20030011709
    Abstract: An inter-frame motion detector detects the presence or absence of motion between frames on the basis of judgment whether or not an inter-frame difference is not more than a set value. A vertical edge continuity detector calculates difference values between an object pixel and pixels above or below the object pixel in an inlaid picture, and detects whether or not there is horizontal continuity of an inter-field vertical edge on the basis of judgment whether or not the signs of the difference values are the same continuously over not less than a predetermined number of pixels, in the horizontal direction, including the object pixel. When it is detected that there is no motion between frames, and it is detected that there is horizontal continuity of the inter-field vertical edge, it is judged that a picture is in a completely still state.
    Type: Application
    Filed: August 20, 2002
    Publication date: January 16, 2003
    Inventors: Mitsuhiro Kasahara, Tomoaki Daigi, Hideaki Kawamura
  • Publication number: 20030011708
    Abstract: A binarizer binarizes a video signal VD1 inputted from an A/D converter and a video signal VD2 outputted from a line memory using an average luminance value LU fed from a detection window video signal processor as a threshold value, to output a binary pattern BI. A reference pattern generator generates a plurality of reference patterns RA. A first pattern matching angle detector compares the binary pattern BI with each of the plurality of reference patterns RA, to output the angle of the reference pattern RA which matches with the binary pattern BI as angle information PA. A detected isolation point remover 4 outputs angle signal AN when the angle information PA has continuity.
    Type: Application
    Filed: August 2, 2002
    Publication date: January 16, 2003
    Inventors: Hideaki Kawamura, Mitsuhiro Kasahara, Tomoaki Daigi