Patents by Inventor Tomoaki Inokuchi

Tomoaki Inokuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10902900
    Abstract: A magnetic memory device includes a conductive member, a stacked body, and a controller. The stacked body includes a first magnetic layer, a second magnetic layer provided between the conductive member and the first magnetic layer, and a third magnetic layer stacked with the first magnetic layer and the second magnetic layer. The controller causes a current to flow in the conductive member. The controller causes a current to flow between the conductive member and the stacked body. The controller is able to identify three or more levels of an electrical resistance value of the stacked body.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: January 26, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Koui, Hiroaki Yoda, Tomoaki Inokuchi, Naoharu Shimomura, Hideyuki Sugiyama
  • Patent number: 10896708
    Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first element portion, and a controller. The conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first element portion includes a first element, a first interconnect, and a first circuit. The first element includes a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The first counter magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first counter magnetic layer and the first magnetic layer. The first interconnect is electrically connected to the first magnetic layer. The first circuit is electrically connected to the first interconnect. The first circuit includes a first switch, a first capacitance element, a first parallel switch, and a first parallel capacitance element.
    Type: Grant
    Filed: January 13, 2020
    Date of Patent: January 19, 2021
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomoaki Inokuchi, Katsuhiko Koui, Naoharu Shimomura, Hideyuki Sugiyama, Kazutaka Ikegami, Susumu Takeda, Satoshi Takaya, Shinobu Fujita, Hiroaki Yoda
  • Patent number: 10797229
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first to fourth magnetic layers, first and second intermediate layers, and a controller. The conductive layer includes first, to fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first intermediate layer is provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the fourth portion and the third magnetic layer. The second intermediate layer is provided between the third and fourth magnetic layers. The controller is electrically connected to the first and second portions. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.
    Type: Grant
    Filed: May 28, 2019
    Date of Patent: October 6, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Altansargai Buyandalai, Satoshi Shirotori, Yuichi Ohsawa, Hideyuki Sugiyama, Mariko Shimizu, Hiroaki Yoda, Tomoaki Inokuchi
  • Patent number: 10783947
    Abstract: According to one embodiment, a magnetic memory device includes a first member, a first memory cell, and a controller. The first member includes first, second, and third regions. The first memory cell includes first and second magnetic layers, and a first nonmagnetic layer. The second magnetic layer is provided between the third region and the first magnetic layer. The first nonmagnetic layer is provided between the first and second magnetic layers. The controller is electrically connected to the first and second regions, and the first magnetic layer. The controller programs first information to the first memory cell by setting the first magnetic layer to a first electric potential. The controller programs second information to the first memory cell by setting the first magnetic layer to a second electric potential. The second electric potential is different from the first electric potential. The second information is different from the first information.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: September 22, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiko Koui, Hiroaki Yoda, Tomoaki Inokuchi, Naoharu Shimomura
  • Publication number: 20200279596
    Abstract: According to one embodiment, a magnetic memory device includes a conductive member, a first element portion, and a controller. The conductive member includes a first portion, a second portion, and a third portion between the first portion and the second portion. The first element portion includes a first element, a first interconnect, and a first circuit. The first element includes a first magnetic layer, a first counter magnetic layer, and a first nonmagnetic layer. The first counter magnetic layer is provided between the third portion and the first magnetic layer. The first nonmagnetic layer is provided between the first counter magnetic layer and the first magnetic layer. The first interconnect is electrically connected to the first magnetic layer. The first circuit is electrically connected to the first interconnect. The first circuit includes a first switch, a first capacitance element, a first parallel switch, and a first parallel capacitance element.
    Type: Application
    Filed: January 13, 2020
    Publication date: September 3, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoaki INOKUCHI, Katsuhiko KOUI, Naoharu SHIMOMURA, Hideyuki SUGIYAMA, Kazutaka IKEGAMI, Susumu TAKEDA, Satoshi TAKAYA, Shinobu FUJITA, Hiroaki YODA
  • Publication number: 20200090718
    Abstract: A magnetic memory device includes a conductive member, a stacked body, and a controller. The stacked body includes a first magnetic layer, a second magnetic layer provided between the conductive member and the first magnetic layer, and a third magnetic layer stacked with the first magnetic layer and the second magnetic layer. The controller causes a current to flow in the conductive member. The controller causes a current to flow between the conductive member and the stacked body. The controller is able to identify three or more levels of an electrical resistance value of the stacked body.
    Type: Application
    Filed: March 13, 2019
    Publication date: March 19, 2020
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuhiko KOUI, Hiroaki Yoda, Tomoaki Inokuchi, Naoharu Shimomura, Hideyuki Sugiyama
  • Patent number: 10529399
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The conductive layer includes a first region, a second region, and a third region between the first region and the second region. The second magnetic layer is provided between the third region and the first magnetic layer in a first direction crossing a second direction. The second direction is from the first region toward the second region. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer. The third region includes first and second end portions. The first end portion includes a first protrusion. The second end portion includes a second protrusion. A first position along the second direction of the first protrusion is different from a second position along the second direction of the second protrusion.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 7, 2020
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Ohsawa, Mariko Shimizu, Satoshi Shirotori, Hideyuki Sugiyama, Altansargai Buyandalai, Hiroaki Yoda, Katsuhiko Koui, Tomoaki Inokuchi, Naoharu Shimomura
  • Patent number: 10490736
    Abstract: A magnetic memory according to an embodiment includes: first to third terminals; a nonmagnetic conductive layer including first to third regions, the second region being disposed between the first and third regions, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; and a magnetoresistive element disposed to correspond to the second region, including a first magnetic layer electrically connected to the third terminal, a second magnetic layer disposed between the first magnetic layer and the second region, and a nonmagnetic layer disposed between the first and second magnetic layers, the conductive layer including at least one of an alloy including Ir and Ta, an alloy including Ir and V, an alloy including Au and V, an alloy including Au and Nb, or an alloy including Pt and V, each of the alloys having an fcc structure.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: November 26, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Saito, Tomoaki Inokuchi, Yushi Kato, Soichi Oikawa, Mizue Ishikawa, Hiroaki Yoda
  • Patent number: 10460784
    Abstract: According to one embodiment, a magnetic memory includes: a memory cell including a first magnetoresistive effect element; a reference circuit including a second magnetoresistive effect element having a first resistance state and a third magnetoresistive effect element having a second resistance state; and a read circuit configured to read data in the memory cell based on a first signal based on an output from the memory cell and a second signal based on an output from the reference circuit. At a time of reading of the data, a first voltage is applied to the first magnetoresistive effect element, and a second voltage higher than the first voltage is applied to the second magnetoresistive effect element and the third magnetoresistive effect element.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: October 29, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazutaka Ikegami, Tomoaki Inokuchi, Satoshi Takaya, Shinobu Fujita
  • Publication number: 20190295619
    Abstract: According to one embodiment, a magnetic device includes: a first conductive layer; a first magnetoresistive effect element disposed on the first S conductive layer and including a first control terminal; and a first circuit configured to supply a first current in a first direction into the first conductive layer and apply a first control voltage to the first control terminal of the first magnetoresistive effect element, wherein in a case in which the first current is supplied to the first conductive layer, the first magnetoresistive effect element holds a value corresponding to a logical disjunction between a first value of first data in the first magnetoresistive effect element and a second value of the first control voltage corresponding to second data.
    Type: Application
    Filed: September 17, 2018
    Publication date: September 26, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Tomoaki INOKUCHI, Naoharu SHIMOMURA, Katsuhiko KOUI, Yuuzo KAMIGUCHI, Kazutaka IKEGAMI, Shinobu FUJITA, Hiroaki YODA
  • Publication number: 20190295621
    Abstract: According to one embodiment, a magnetic memory includes: a memory cell including a first magnetoresistive effect element; a reference circuit including a second magnetoresistive effect element having a first resistance state and a third magnetoresistive effect element having a second resistance state; and a read circuit configured to read data in the memory cell based on a first signal based on an output from the memory cell and a second signal based on an output from the reference circuit. At a time of reading of the data, a first voltage is applied to the first magnetoresistive effect element, and a second voltage higher than the first voltage is applied to the second magnetoresistive effect element and the third magnetoresistive effect element.
    Type: Application
    Filed: August 31, 2018
    Publication date: September 26, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kazutaka IKEGAMI, Tomoaki Inokuchi, Satoshi Takaya, Shinobu Fujita
  • Publication number: 20190287597
    Abstract: According to one embodiment, a magnetic memory device includes a first member, a first memory cell, and a controller. The first member includes first, second, and third regions. The first memory cell includes first and second magnetic layers, and a first nonmagnetic layer. The second magnetic layer is provided between the third region and the first magnetic layer. The first nonmagnetic layer is provided between the first and second magnetic layers. The controller is electrically connected to the first and second regions, and the first magnetic layer. The controller programs first information to the first memory cell by setting the first magnetic layer to a first electric potential. The controller programs second information to the first memory cell by setting the first magnetic layer to a second electric potential. The second electric potential is different from the first electric potential. The second information is different from the first information.
    Type: Application
    Filed: August 31, 2018
    Publication date: September 19, 2019
    Applicant: Kabushiki Kaisaha Toshiba
    Inventors: Katsuhiko KOUI, Hiroaki Yoda, Tomoaki Inokuchi, Naoharu Shimomura
  • Publication number: 20190279699
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer. The conductive layer includes a first region, a second region, and a third region between the first region and the second region. The second magnetic layer is provided between the third region and the first magnetic layer in a first direction crossing a second direction. The second direction is from the first region toward the second region. The first nonmagnetic layer is provided between the first magnetic layer and the second magnetic layer. The third region includes first and second end portions. The first end portion includes a first protrusion. The second end portion includes a second protrusion. A first position along the second direction of the first protrusion is different from a second position along the second direction of the second protrusion.
    Type: Application
    Filed: August 21, 2018
    Publication date: September 12, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yuichi Ohsawa, Mariko Shimizu, Satoshi Shirotori, Hideyuki Sugiyama, Altansargai Buyandalai, Hiroaki Yoda, Katsuhiko Koui, Tomoaki Inokuchi, Naoharu Shimomura
  • Publication number: 20190280189
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first to fourth magnetic layers, first and second intermediate layers, and a controller. The conductive layer includes first, to fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first intermediate layer is provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the fourth portion and the third magnetic layer. The second intermediate layer is provided between the third and fourth magnetic layers. The controller is electrically connected to the first and second portions. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.
    Type: Application
    Filed: May 28, 2019
    Publication date: September 12, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Altansargai BUYANDALAI, Satoshi SHIROTORI, Yuichi OHSAWA, Hideyuki SUGIYAMA, Mariko SHIMIZU, Hiroaki YODA, Tomoaki INOKUCHI
  • Patent number: 10410707
    Abstract: According to one embodiment, a nonvolatile memory includes a conductive line including a first portion, a second portion and a third portion therebetween, a storage element including a first magnetic layer, a second magnetic layer and a nonmagnetic layer therebetween, and the first magnetic layer being connected to the third portion, and a circuit flowing a write current between the first and second portions, applying a first potential to the second magnetic layer, and blocking the write current flowing between the first and second portions after changing the second magnetic layer from the first potential to a second potential.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: September 10, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoaki Inokuchi, Naoharu Shimomura, Katsuhiko Koui, Yuuzo Kamiguchi, Satoshi Shirotori, Kazutaka Ikegami, Hiroaki Yoda
  • Patent number: 10361358
    Abstract: A magnetic memory includes: first to fourth wirings; first and second terminals; a first conductive layer including first to third regions, the second region being between the first region and the third region, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; a first magnetoresistive element including a first and a second magnetic layer, and a first nonmagnetic layer disposed between the first and the magnetic layer; a first transistor including a third terminal electrically connected to the first magnetic layer, a fourth terminal electrically connected to the third wiring, and a first control terminal electrically connected to the first wiring; and a second transistor including a fifth terminal electrically connected to the first terminal, a sixth terminal electrically connected to the second wiring, and a second control terminal electrically connected to the first wiring.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 23, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Keiko Abe, Kazutaka Ikegami, Shinobu Fujita, Katsuhiko Koui, Tomoaki Inokuchi, Satoshi Shirotori, Yuichi Ohsawa, Hideyuki Sugiyama, Hiroaki Yoda, Naoharu Shimomura, Yuuzo Kamiguchi
  • Patent number: 10347820
    Abstract: According to one embodiment, a magnetic memory device includes a conductive layer, first to fourth magnetic layers, first and second intermediate layers, and a controller. The conductive layer includes first, to fifth portions. The first magnetic layer is separated from the third portion. The second magnetic layer is provided between the third portion and the first magnetic layer. The first intermediate layer is provided between the first and second magnetic layers. The third magnetic layer is separated from the fourth portion. The fourth magnetic layer is provided between the fourth portion and the third magnetic layer. The second intermediate layer is provided between the third and fourth magnetic layers. The controller is electrically connected to the first and second portions. The controller implements a first operation of supplying a first current to the conductive layer, and a second operation of supplying a second current to the conductive layer.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: July 9, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Altansargai Buyandalai, Satoshi Shirotori, Yuichi Ohsawa, Hideyuki Sugiyama, Mariko Shimizu, Hiroaki Yoda, Tomoaki Inokuchi
  • Patent number: 10347313
    Abstract: According to one embodiment, a magnetic memory includes: magnetoresistive effect elements arranged on an conductive layer; and a first circuit which passes a write current through the conductive layer and applies a control voltage to the magnetoresistive effect elements, to write data including a first value and a second value into the magnetoresistive effect elements. The first circuit adjusts at least one of a write sequence of the first value and the second value, a current value of the write current, and a pulse width of the write current, on the basis of an arrangement of the first value and the second value in the data.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: July 9, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Naoharu Shimomura, Tomoaki Inokuchi, Katsuhiko Koui, Yuzo Kamiguchi, Hiroaki Yoda, Hideyuki Sugiyama
  • Patent number: 10283697
    Abstract: A magnetic memory according to an embodiment includes: a magnetoresistive device including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer between the first magnetic layer and the second magnetic layer; a first wiring electrically connected to the first magnetic layer; a second wiring that is electrically connected to the second magnetic layer and contains an antiferromagnetic material; a third wiring crossing the second wiring; an insulating layer between the second wiring and the third wiring; a first write circuit for applying a voltage between the second wiring and the third wiring; and a read circuit electrically connected to the first wiring and the second wiring.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: May 7, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tomoaki Inokuchi, Mizue Ishikawa, Hideyuki Sugiyama, Yoshiaki Saito
  • Publication number: 20190088860
    Abstract: A magnetic memory according to an embodiment includes: first to third terminals; a nonmagnetic conductive layer including first to third regions, the second region being disposed between the first and third regions, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; and a magnetoresistive element disposed to correspond to the second region, including a first magnetic layer electrically connected to the third terminal, a second magnetic layer disposed between the first magnetic layer and the second region, and a nonmagnetic layer disposed between the first and second magnetic layers, the conductive layer including at least one of an alloy including Ir and Ta, an alloy including Ir and V, an alloy including Au and V, an alloy including Au and Nb, or an alloy including Pt and V, each of the alloys having an fcc structure.
    Type: Application
    Filed: March 6, 2018
    Publication date: March 21, 2019
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoshiaki Saito, Tomoaki Inokuchi, Yushi Kato, Soichi Oikawa, Mizue Ishikawa, Hiroaki Yoda