Patents by Inventor Tomoe Yamamoto

Tomoe Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240109054
    Abstract: Disclosed is a method for reproducing water-absorbing resin particles including: treating water-absorbing resin particles that have absorbed water with hot water; and treating the water-absorbing resin particles after the hot water treatment with a hydrophilic organic solvent.
    Type: Application
    Filed: October 15, 2020
    Publication date: April 4, 2024
    Inventor: Tomoe YAMAMOTO
  • Publication number: 20230347318
    Abstract: Provided is a water-absorbing resin composition that is capable of achieving both high liquid diffusion and liquid leakage prevention in an absorbent. The present invention provides a water-absorbing resin composition, wherein: an electromotive force P(mV) of a first-washing washing liquid, obtained as a result of washing the water-absorbing resin composition by means of the washing method indicated below, is equal to or greater than 80 V; and the difference (P?Q) between the electromotive force P(mV) and an electromotive force Q(mV) of a second-washing washing liquid, obtained as a result of washing the water-absorbing resin composition by means of the washing method indicated below, is equal to or greater than 10 mV. (Washing method) A container in which a sieve having a mesh size of 36 ?m is attached to the bottom of a cylinder having an inner diameter of 60 mm is prepared. 1 g of the water-absorbing resin composition is evenly dispersed on the sieve in the container.
    Type: Application
    Filed: July 15, 2021
    Publication date: November 2, 2023
    Inventor: Tomoe YAMAMOTO
  • Publication number: 20230182112
    Abstract: A particulate water-absorbing resin composition having excellent flowability is provided. The particulate water-absorbing resin composition comprises a hydrazide compound and a water-absorbing resin.
    Type: Application
    Filed: April 23, 2021
    Publication date: June 15, 2023
    Inventor: Tomoe YAMAMOTO
  • Publication number: 20210138434
    Abstract: Provided is a sandbag which is unlikely to break down even when using water-absorbing resin particles therein. A sandbag having a water-permeable bag and water-absorbing resin particles stored in the bag, wherein the pure-water absorption factor of the water-absorbing resin particles is at least a factor of 1,000, and the compression-breaking stress of the water-absorbing resin particles when swollen with pure water is at least 0.1N.
    Type: Application
    Filed: March 27, 2019
    Publication date: May 13, 2021
    Applicant: Sumitomo Seiko Chemicals Co., Ltd.
    Inventors: Tomoe YAMAMOTO, Toshihiko KANKI
  • Publication number: 20210022965
    Abstract: Provided is an exfoliator which absorbs water and exhibits suitable hardness, provides little skin stimulation, and has a favorable skin massaging effect. The exfoliator exhibits a pure-water absorption factor of at least 30 times, and exhibits a compression-breaking stress of 0.14-1.40 N upon absorbing water and swelling to 30 times the initial mass thereof.
    Type: Application
    Filed: March 27, 2019
    Publication date: January 28, 2021
    Inventors: Tomoe Yamamoto, Toshihiko Kanki
  • Publication number: 20140327064
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Application
    Filed: July 16, 2014
    Publication date: November 6, 2014
    Inventors: Toshihiro IIZUKA, Tomoe YAMAMOTO, Mami TODA, Shintaro YAMAMICHI
  • Patent number: 8815678
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Grant
    Filed: October 30, 2007
    Date of Patent: August 26, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Patent number: 8304021
    Abstract: A vapor phase deposition apparatus 100 for forming a thin film comprising a chamber 1060, a piping unit 120 for supplying a source material of the thin film into the chamber 1060 in a gaseous condition, a vaporizer 202 for vaporizing the source material in a source material container 112 and supplying the vaporized gas in the piping unit 120 and a temperature control unit 180, is presented.
    Type: Grant
    Filed: September 17, 2009
    Date of Patent: November 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoe Yamamoto, Tomohisa Iino
  • Publication number: 20120261735
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO.sub.2, HfO.sub.2, (Zr.sub.x, Hf.sub.1?x)O.sub.2 (0<x<1), (Zr.sub.y, Ti.sub.1?y)O.sub.2 (0<y<1), (Hf.sub.z, Ti.sub.1?z)O.sub.2 (0<z<1), (Zr.sub.k, Ti.sub.l, Hf.sub.m)O.sub.2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Application
    Filed: June 29, 2012
    Publication date: October 18, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiro IIZUKA, Tomoe YAMAMOTO, Mami TODA, Shintaro YAMAMICHI
  • Patent number: 8212299
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1?x)O2(0<x<1), (Zry, Ti1?y)O2(0<y<1), (Hfz, Ti1?z)O2(0<z<1), (Zrk,Til, Hfm)O2(0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: July 3, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Patent number: 8169013
    Abstract: A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source and drain regions and a capacitor, the capacitor being of a MIM structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, the capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, Hf92, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)o2 (0<y<1), (Hfz, Ti1-z)92 (0<z<1 and (Zrk, Til, Hfm)o2 (0<k, l, m<1, k+l+m?1), wherein each of the first and second transistors has a refractory metal silicide layer formed over each of the source and drain regions thereof and the lower metal electrode is connected through a metal plug to the refractory metal silicide layer formed over one o
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: May 1, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Patent number: 7943475
    Abstract: There is provided a semiconductor device comprising a dielectric film made of a high dielectric constant material, in which a leak current is reduced in the film and which exhibits improved device reliability. Specifically, a dielectric film 142 is a metal-compound film having a composition represented by the formula MOxCyNz wherein x, y and z meet the conditions: 0<x, 0.1?y?1.25, 0.01?z and x+y+z=2; and M comprises at least Hf or Zr.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: May 17, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tomoe Yamamoto, Toshihiro Iizuka
  • Publication number: 20100003832
    Abstract: A vapor phase deposition apparatus 100 for forming a thin film comprising a chamber 1060, a piping unit 120 for supplying a source material of the thin film into the chamber 1060 in a gaseous condition, a vaporizer 202 for vaporizing the source material in a source material container 112 and supplying the vaporized gas in the piping unit 120 and a temperature control unit 180, is presented.
    Type: Application
    Filed: September 17, 2009
    Publication date: January 7, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tomoe YAMAMOTO, Tomohisa IINO
  • Patent number: 7608502
    Abstract: In the process for manufacturing a semiconductor device of the present invention, a capacitor dielectric film is deposited via an atomic layer deposition employing an organic source material containing one or more metallic element(s) selected from the group consisting of Zr, Hf, La and Y as a deposition gas. The process for manufacturing a capacitor of the present invention includes obtaining a boundary temperature T (degree C.), at which an increase in a deposition rate for depositing the capacitor dielectric film as increasing the temperature is detected, on the basis of a correlation data of a deposition temperature in the atomic layer deposition employing the deposition gas with a deposition rate for depositing the capacitor dielectric film at the deposition temperature (S100 and S102); and depositing the capacitor dielectric film via the atomic layer deposition employing the deposition gas at a temperature within a range of from (T?20) (degree C.) to (T+20) (degree C.) (S104 to S112).
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: October 27, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Tomohisa Iino, Naomi Fukumaki, Yoshitake Kato, Tomoe Yamamoto
  • Patent number: 7439181
    Abstract: A method for depositing a metal compound film on the wafer by using a vapor phase deposition apparatus 100, including: forming a thin film on the wafer in an interior of the vapor phase deposition apparatus 100 by introducing a source gas for the metal compound film containing Hf or Zr; unloading the wafer having the metal compound film formed thereon from the interior of the vapor phase deposition apparatus 100; introducing a reactive gas in the interior of the vapor phase deposition apparatus 100 to immobilize the unreacted organic compound 180 derived from the source gas remained in the interior of the vapor phase deposition apparatus 100; loading another wafer in the interior of the vapor phase deposition apparatus 100; and depositing metal compound film on another wafer by further introducing the source gas in the interior of the vapor phase deposition apparatus 100, in the condition that the unreacted organic compound 180 exists therein as an immobilized form, is presented.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: October 21, 2008
    Assignee: NEC Electronics Corporation
    Inventor: Tomoe Yamamoto
  • Publication number: 20080064147
    Abstract: In a thin film transistor, each of an upper electrode and a lower electrode is formed of at least one material selected from the group consisting of a metal and a metal nitride, represented by TiN, Ti, W, WN, Pt, Ir, Ru. A capacitor dielectric film is formed of at least one material selected from the group consisting of ZrO2, HfO2, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)O2 (0<y<1), (Hfz, Ti1-z)O2 (0<z<1), (Zrk, Til, Hfm)O2 (0<k, l, m<1, k+l+m=1), by an atomic layer deposition process. The thin film transistor thus formed has a minimized leakage current and an increased capacitance.
    Type: Application
    Filed: October 30, 2007
    Publication date: March 13, 2008
    Applicant: NEC CORPORATION
    Inventors: Toshihiro IIZUKA, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Publication number: 20070289610
    Abstract: A method for depositing a metal compound film on the wafer by using a vapor phase deposition apparatus 100, including: forming a thin film on the wafer in an interior of the vapor phase deposition apparatus 100 by introducing a source gas for the metal compound film containing Hf or Zr; unloading the wafer having the metal compound film formed thereon from the interior of the vapor phase deposition apparatus 100; introducing a reactive gas in the interior of the vapor phase deposition apparatus 100 to immobilize the unreacted organic compound 180 derived from the source gas remained in the interior of the vapor phase deposition apparatus 100; loading another wafer in the interior of the vapor phase deposition apparatus 100; and depositing metal compound film on another wafer by further introducing the source gas in the interior of the vapor phase deposition apparatus 100, in the condition that the unreacted organic compound 180 exists therein as an immobilized form, is presented.
    Type: Application
    Filed: August 21, 2007
    Publication date: December 20, 2007
    Applicant: NEC ELECTRONICS CORPORATION
    Inventor: Tomoe YAMAMOTO
  • Patent number: 7276444
    Abstract: A method for depositing a metal compound film on the wafer by using a vapor phase deposition apparatus 100, including: forming a thin film on the wafer in an interior of the vapor phase deposition apparatus 100 by introducing a source gas for the metal compound film containing Hf or Zr; unloading the wafer having the metal compound film formed thereon from the interior of the vapor phase deposition apparatus 100; introducing a reactive gas in the interior of the vapor phase deposition apparatus 100 to immobilize the unreacted organic compound 180 derived from the source gas remained in the interior of the vapor phase deposition apparatus 100; loading another wafer in the interior of the vapor phase deposition apparatus 100; and depositing metal compound film on another wafer by further introducing the source gas in the interior of the vapor phase deposition apparatus 100, in the condition that the unreacted organic compound 180 exists therein as an immobilized form, is presented.
    Type: Grant
    Filed: June 1, 2005
    Date of Patent: October 2, 2007
    Assignee: NEC Electronics Corporation
    Inventor: Tomoe Yamamoto
  • Publication number: 20070152256
    Abstract: A semiconductor device having a logic section and a memory section that are formed on the same semiconductor chip, including: a first transistor formed in the logic section and having gate electrodes and source and drain regions, and a second transistor formed in the memory section having gate electrodes, source and drain regions and a capacitor, the capacitor being of a MIM structure and having an upper and a lower metal electrode and a capacitor dielectric film sandwiched therebetween, the capacitor dielectric film being formed of a dielectric material which is selected from the group consisting of ZrO2, Hf92, (Zrx, Hf1-x)O2 (0<x<1), (Zry, Ti1-y)o2 (0<y<1), (Hfz, Ti1-z)92 (0<z<1 and (Zrk, Til, Hfm)o2 (0<k, l, m<1, k+l+m?1), wherein each of the first and second transistors has a refractory metal silicide layer formed over each of the source and drain regions thereof and the lower metal electrode is connected through a metal plug to the refractory metal silicide layer formed over one o
    Type: Application
    Filed: December 12, 2006
    Publication date: July 5, 2007
    Inventors: Toshihiro Iizuka, Tomoe Yamamoto, Mami Toda, Shintaro Yamamichi
  • Publication number: 20060121671
    Abstract: There is provided a semiconductor device comprising a dielectric film made of a high dielectric constant material, in which a leak current is reduced in the film and which exhibits improved device reliability. Specifically, a dielectric film 142 is a metal-compound film having a composition represented by the formula MOxCyNz wherein x, y and z meet the conditions: 0<x, 0.1?y?1.25, 0.01?z and x+y+z=2; and M comprises at least Hf or Zr.
    Type: Application
    Filed: January 4, 2006
    Publication date: June 8, 2006
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tomoe Yamamoto, Toshihiro Iizuka