Patents by Inventor Tomoharu Ogita

Tomoharu Ogita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12072416
    Abstract: The present technology relates to a light-receiving element and a distance-measuring module. A light-receiving element includes an on-chip lens, a wiring layer, and a semiconductor layer arranged between the on-chip lens and the wiring layer, the semiconductor layer includes a first voltage application portion to which a first voltage is applied, a second voltage application portion to which a second voltage different from the first voltage is applied, a first charge detection portion arranged around the first voltage application portion, a second charge detection portion arranged around the second voltage application portion, and a pixel separation portion that separates the semiconductor layer at least up to a predetermined depth in a boundary portion of adjacent pixels, and a third voltage is applied to the pixel separation portion. The present technology can be applied to, for example, a light-receiving element that generates distance information by a ToF method.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: August 27, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Tomoharu Ogita
  • Publication number: 20240055456
    Abstract: A solid-state imaging device according to an embodiment includes: a plurality of pixels, each of the plurality of pixels including a substrate having a first surface serving as a light incident surface, a photoelectric conversion unit located inside the substrate, a light shielding unit provided on a first surface side, the light shielding unit having a hole portion configured to allow light to be incident on the photoelectric conversion unit, and a first lens made of silicon, the first lens being provided on the light shielding unit and condensing incident light toward the hole portion.
    Type: Application
    Filed: August 13, 2021
    Publication date: February 15, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shinichiro NOUDO, Tomohiro YAMAZAKI, Yoshiki EBIKO, Sozo YOKOGAWA, Tomoharu OGITA, Hiroyasu MATSUGAI, Yusuke MORIYA
  • Patent number: 11715751
    Abstract: The present technology relates a solid-state imaging element, an electronic apparatus, and a semiconductor device each of which enables deterioration of electrical characteristics in a well region of a semiconductor element formed in a thinned semiconductor substrate to be restrained. A solid-state imaging element as a first aspect of the present technology is a solid-state imaging element constituted by laminating semiconductor substrates in three or more layers, in which of the laminated semiconductor substrates, at least one sheet of the semiconductor substrate is thinned, and an impurity region whose carrier type is the same as that of the thinned semiconductor substrate is formed between a well region and a thinned surface portion in the thinned semiconductor substrate. The present technology can, for example, be applied to a CMOS image sensor.
    Type: Grant
    Filed: May 10, 2021
    Date of Patent: August 1, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hidenobu Tsugawa, Tomoharu Ogita
  • Patent number: 11570387
    Abstract: The present disclosure relates to a solid-state imaging device, a method for manufacturing the same, and an electronic apparatus capable of improving sensitivity while suppressing degradation of color mixture. The solid-state imaging device includes an anti-reflection portion having a moth-eye structure provided on a boundary surface on a light-receiving surface side of a photoelectric conversion region of each pixel arranged two-dimensionally, and an inter-pixel light-blocking portion provided below the boundary surface of the anti-reflection portion to block incident light. In addition, the photoelectric conversion region is a semiconductor region, and the inter-pixel light-blocking portion has a trench structure obtained by digging the semiconductor region in a depth direction at a pixel boundary. The techniques according to the present disclosure can be applied to, for example, a solid-state imaging device of a rear surface irradiation type.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: January 31, 2023
    Assignee: SONY GROUP CORPORATION
    Inventors: Yoshiaki Masuda, Yuki Miyanami, Hideshi Abe, Tomoyuki Hirano, Masanari Yamaguchi, Yoshiki Ebiko, Kazufumi Watanabe, Tomoharu Ogita
  • Publication number: 20220293658
    Abstract: The present technology relates to a light receiving element, a distance measurement module, and electronic equipment which are capable of reducing leakage of incident light to adjacent pixels. The light receiving element includes an on-chip lens, a wiring layer, and a semiconductor layer which is disposed between the on-chip lens and the wiring layer and includes a photodiode. The wiring layer includes a reflection film which is disposed such that at least a portion thereof overlaps the photodiode when seen in a plan view, and a transfer transistor which reads charge generated by the photodiode, and the reflection film is formed of a material different from that of a metal wiring electrically connected to a gate of the transfer transistor. The present technology can be applied to, for example, a distance measurement module that measures a distance to a subject, and the like.
    Type: Application
    Filed: October 16, 2020
    Publication date: September 15, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yutaro KOMURO, Yoshiki EBIKO, Tomoharu OGITA
  • Patent number: 11362126
    Abstract: The present technology relates to a light reception device and a distance measurement module. The light reception device includes an on-chip lens, a wiring layer, and a semiconductor layer between the on-chip lens and the wiring layer. The semiconductor layer includes a first voltage application portion to which a first voltage is applied, a second voltage application portion to which a second voltage different from the first voltage is applied, a first charge detection portion, a second charge detection portion, and a through electrode extending through the semiconductor layer. The light reception device is configured such that a third voltage is applied through the through electrode to a film formed on a face of the semiconductor layer on the on-chip lens side. The present technology can be applied to a light reception device that generates distance information, for example, by a ToF method or the like.
    Type: Grant
    Filed: July 4, 2019
    Date of Patent: June 14, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Tomoharu Ogita
  • Patent number: 11362123
    Abstract: The present technology relates to an imaging device, a camera module, and an electronic apparatus that make it possible to reduce a profile of the camera module and to enhance sensitivity. The imaging device includes: a semiconductor substrate in which a light receiving section is formed that includes a plurality of pixels performing photoelectric conversion; and a reinforcing member that is disposed on side of the light receiving section of the semiconductor substrate and includes an opening in which a part opposed to the light receiving section is opened. The present technology is applicable to, for example, an imaging device that captures an image, a camera module that focuses light to capture an image, an electronic apparatus equipped with a camera function, a vehicle control system that is mounted on a vehicle, an endoscopic surgery system that is used in an endoscopic surgery, and the like.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: June 14, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Tomoharu Ogita
  • Publication number: 20220150429
    Abstract: The present disclosure relates to a solid-state imaging device, a method for manufacturing the same, and an electronic apparatus capable of improving sensitivity while suppressing degradation of color mixture. The solid-state imaging device includes an anti-reflection portion having a moth-eye structure provided on a boundary surface on a light-receiving surface side of a photoelectric conversion region of each pixel arranged two-dimensionally, and an inter-pixel light-blocking portion provided below the boundary surface of the anti-reflection portion to block incident light. In addition, the photoelectric conversion region is a semiconductor region, and the inter-pixel light-blocking portion has a trench structure obtained by digging the semiconductor region in a depth direction at a pixel boundary. The techniques according to the present disclosure can be applied to, for example, a solid-state imaging device of a rear surface irradiation type.
    Type: Application
    Filed: January 26, 2022
    Publication date: May 12, 2022
    Applicant: SONY GROUP CORPORATION
    Inventors: Yoshiaki MASUDA, Yuki MIYANAMI, Hideshi ABE, Tomoyuki HIRANO, Masanari YAMAGUCHI, Yoshiki EBIKO, Kazufumi WATANABE, Tomoharu OGITA
  • Patent number: 11277578
    Abstract: The present disclosure relates to a solid-state imaging device, a method for manufacturing the same, and an electronic apparatus capable of improving sensitivity while suppressing degradation of color mixture. The solid-state imaging device includes an anti-reflection portion having a moth-eye structure provided on a boundary surface on a light-receiving surface side of a photoelectric conversion region of each pixel arranged two-dimensionally, and an inter-pixel light-blocking portion provided below the boundary surface of the anti-reflection portion to block incident light. In addition, the photoelectric conversion region is a semiconductor region, and the inter-pixel light-blocking portion has a trench structure obtained by digging the semiconductor region in a depth direction at a pixel boundary. The techniques according to the present disclosure can be applied to, for example, a solid-state imaging device of a rear surface irradiation type.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: March 15, 2022
    Assignee: SONY CORPORATION
    Inventors: Yoshiaki Masuda, Yuki Miyanami, Hideshi Abe, Tomoyuki Hirano, Masanari Yamaguchi, Yoshiki Ebiko, Kazufumi Watanabe, Tomoharu Ogita
  • Publication number: 20210293956
    Abstract: The present technology relates to a light-receiving element and a distance-measuring module. A light-receiving element includes an on-chip lens, a wiring layer, and a semiconductor layer arranged between the on-chip lens and the wiring layer, the semiconductor layer includes a first voltage application portion to which a first voltage is applied, a second voltage application portion to which a second voltage different from the first voltage is applied, a first charge detection portion arranged around the first voltage application portion, a second charge detection portion arranged around the second voltage application portion, and a pixel separation portion that separates the semiconductor layer at least up to a predetermined depth in a boundary portion of adjacent pixels, and a third voltage is applied to the pixel separation portion. The present technology can be applied to, for example, a light-receiving element that generates distance information by a ToF method.
    Type: Application
    Filed: July 4, 2019
    Publication date: September 23, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Tomoharu OGITA
  • Publication number: 20210265409
    Abstract: The present technology relates a solid-state imaging element, an electronic apparatus, and a semiconductor device each of which enables deterioration of electrical characteristics in a well region of a semiconductor element formed in a thinned semiconductor substrate to be restrained. A solid-state imaging element as a first aspect of the present technology is a solid-state imaging element constituted by laminating semiconductor substrates in three or more layers, in which of the laminated semiconductor substrates, at least one sheet of the semiconductor substrate is thinned, and an impurity region whose carrier type is the same as that of the thinned semiconductor substrate is formed between a well region and a thinned surface portion in the thinned semiconductor substrate. The present technology can, for example, be applied to a CMOS image sensor.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Inventors: HIDENOBU TSUGAWA, TOMOHARU OGITA
  • Patent number: 11076078
    Abstract: The present disclosure relates to a solid-state imaging device, a method for manufacturing the same, and an electronic apparatus capable of improving sensitivity while suppressing degradation of color mixture. The solid-state imaging device includes an anti-reflection portion having a moth-eye structure provided on a boundary surface on a light-receiving surface side of a photoelectric conversion region of each pixel arranged two-dimensionally, and an inter-pixel light-blocking portion provided below the boundary surface of the anti-reflection portion to block incident light. In addition, the photoelectric conversion region is a semiconductor region, and the inter-pixel light-blocking portion has a trench structure obtained by digging the semiconductor region in a depth direction at a pixel boundary. The techniques according to the present disclosure can be applied to, for example, a solid-state imaging device of a rear surface irradiation type.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: July 27, 2021
    Assignee: SONY CORPORATION
    Inventors: Yoshiaki Masuda, Yuki Miyanami, Hideshi Abe, Tomoyuki Hirano, Masanari Yamaguchi, Yoshiki Ebiko, Kazufumi Watanabe, Tomoharu Ogita
  • Publication number: 20210167114
    Abstract: The present technology relates to a light reception device and a distance measurement module. The light reception device includes an on-chip lens, a wiring layer, and a semiconductor layer between the on-chip lens and the wiring layer. The semiconductor layer includes a first voltage application portion to which a first voltage is applied, a second voltage application portion to which a second voltage different from the first voltage is applied, a first charge detection portion, a second charge detection portion, and a through electrode extending through the semiconductor layer. The light reception device is configured such that a third voltage is applied through the through electrode to a film formed on a face of the semiconductor layer on the on-chip lens side. The present technology can be applied to a light reception device that generates distance information, for example, by a ToF method or the like.
    Type: Application
    Filed: July 4, 2019
    Publication date: June 3, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Tomoharu OGITA
  • Patent number: 11024663
    Abstract: The present technology relates a solid-state imaging element, an electronic apparatus, and a semiconductor device each of which enables deterioration of electrical characteristics in a well region of a semiconductor element formed in a thinned semiconductor substrate to be restrained. A solid-state imaging element as a first aspect of the present technology is a solid-state imaging element constituted by laminating semiconductor substrates in three or more layers, in which of the laminated semiconductor substrates, at least one sheet of the semiconductor substrate is thinned, and an impurity region whose carrier type is the same as that of the thinned semiconductor substrate is formed between a well region and a thinned surface portion in the thinned semiconductor substrate. The present technology can, for example, be applied to a CMOS image sensor.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: June 1, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Hidenobu Tsugawa, Tomoharu Ogita
  • Publication number: 20210075942
    Abstract: The present disclosure relates to a solid-state imaging device, a method for manufacturing the same, and an electronic apparatus capable of improving sensitivity while suppressing degradation of color mixture. The solid-state imaging device includes an anti-reflection portion having a moth-eye structure provided on a boundary surface on a light-receiving surface side of a photoelectric conversion region of each pixel arranged two-dimensionally, and an inter-pixel light-blocking portion provided below the boundary surface of the anti-reflection portion to block incident light. In addition, the photoelectric conversion region is a semiconductor region, and the inter-pixel light-blocking portion has a trench structure obtained by digging the semiconductor region in a depth direction at a pixel boundary. The techniques according to the present disclosure can be applied to, for example, a solid-state imaging device of a rear surface irradiation type.
    Type: Application
    Filed: November 3, 2020
    Publication date: March 11, 2021
    Applicant: SONY CORPORATION
    Inventors: Yoshiaki MASUDA, Yuki MIYANAMI, Hideshi ABE, Tomoyuki HIRANO, Masanari YAMAGUCHI, Yoshiki EBIKO, Kazufumi WATANABE, Tomoharu OGITA
  • Patent number: 10866345
    Abstract: To prevent the resin from oozing out during the lens molding due to the capillary action. A laminated lens structure according to the present disclosure includes: a plurality of lens structures including a substrate provided with an opening part, a lens inserted into the opening part to be fixed to the substrate, and a recessed part provided at an area in which a lateral face of the opening part and a surface of the substrate are intersected, and recessed more than the surface of the substrate. The lenses are arrayed in an optical axis direction by the substrates being joined. This configuration makes it possible to prevent the resin from oozing out during the lens molding due to the capillary action.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: December 15, 2020
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Atsushi Yamamoto, Hiroyasu Matsugai, Kensaku Maeda, Tomoharu Ogita
  • Patent number: 10855893
    Abstract: The present disclosure relates to a solid-state imaging device, a method for manufacturing the same, and an electronic apparatus capable of improving sensitivity while suppressing degradation of color mixture. The solid-state imaging device includes an anti-reflection portion having a moth-eye structure provided on a boundary surface on a light-receiving surface side of a photoelectric conversion region of each pixel arranged two-dimensionally, and an inter-pixel light-blocking portion provided below the boundary surface of the anti-reflection portion to block incident light. In addition, the photoelectric conversion region is a semiconductor region, and the inter-pixel light-blocking portion has a trench structure obtained by digging the semiconductor region in a depth direction at a pixel boundary. The techniques according to the present disclosure can be applied to, for example, a solid-state imaging device of a rear surface irradiation type.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 1, 2020
    Assignee: Sony Corporation
    Inventors: Yoshiaki Masuda, Yuki Miyanami, Hideshi Abe, Tomoyuki Hirano, Masanari Yamaguchi, Yoshiki Ebiko, Kazufumi Watanabe, Tomoharu Ogita
  • Publication number: 20200365640
    Abstract: The present technology relates to an imaging device, a camera module, and an electronic apparatus that make it possible to reduce a profile of the camera module and to enhance sensitivity. The imaging device includes: a semiconductor substrate in which a light receiving section is formed that includes a plurality of pixels performing photoelectric conversion; and a reinforcing member that is disposed on side of the light receiving section of the semiconductor substrate and includes an opening in which a part opposed to the light receiving section is opened. The present technology is applicable to, for example, an imaging device that captures an image, a camera module that focuses light to capture an image, an electronic apparatus equipped with a camera function, a vehicle control system that is mounted on a vehicle, an endoscopic surgery system that is used in an endoscopic surgery, and the like.
    Type: Application
    Filed: August 8, 2018
    Publication date: November 19, 2020
    Inventor: TOMOHARU OGITA
  • Publication number: 20200296263
    Abstract: The present disclosure relates to a solid-state imaging device, a method for manufacturing the same, and an electronic apparatus capable of improving sensitivity while suppressing degradation of color mixture. The solid-state imaging device includes an anti-reflection portion having a moth-eye structure provided on a boundary surface on a light-receiving surface side of a photoelectric conversion region of each pixel arranged two-dimensionally, and an inter-pixel light-blocking portion provided below the boundary surface of the anti-reflection portion to block incident light. In addition, the photoelectric conversion region is a semiconductor region, and the inter-pixel light-blocking portion has a trench structure obtained by digging the semiconductor region in a depth direction at a pixel boundary. The techniques according to the present disclosure can be applied to, for example, a solid-state imaging device of a rear surface irradiation type.
    Type: Application
    Filed: May 28, 2020
    Publication date: September 17, 2020
    Applicant: SONY CORPORATION
    Inventors: Yoshiaki MASUDA, Yuki MIYANAMI, Hideshi ABE, Tomoyuki HIRANO, Masanari YAMAGUCHI, Yoshiki EBIKO, Kazufumi WATANABE, Tomoharu OGITA
  • Patent number: 10777462
    Abstract: To prevent a leakage current in a semiconductor integrated circuit in which a plurality of semiconductor substrates is laminated with a through-silicon via. Into a silicon substrate, one of P-type impurities and N-type impurities is implanted at a predetermined concentration. Into a plurality of channels, the other of the P-type impurities and the N-type impurities is implanted at a higher concentration than the predetermined concentration on one surface of the silicon substrate. An electrode is formed in each of the plurality of channels. Into a well layer, the same impurities as in the silicon substrate are implanted at a higher concentration than the predetermined concentration between the other surface of the silicon substrate and the plurality of channels.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: September 15, 2020
    Assignee: SONY CORPORATION
    Inventor: Tomoharu Ogita