Abstract: Memory devices and methods of manufacturing memory devices are provided. The device and methods described suppress oxidation of metal layers exposed to ambient oxygen. After an opening is formed, a nitridation process occurs to nitridate the surface of the exposed metal layer inside the opening. The nitridated region formed on the surface of metal layer inside the opening works as a barrier layer for oxygen diffusion. In addition, the nitridated region works as an electrode for charge trap memory cells.

Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and an opening formed in the film stack, wherein the opening is filled with a metal dielectric layer, a multi-layer structure and a center filling layer, wherein the metal dielectric layer in the opening is interfaced with the conductive structure.

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.

Abstract: Methods of etching film stacks to form gaps of uniform width are described. A film stack is etched through a hardmask. A conformal liner is deposited in the gap. The bottom of the liner is removed. The film stack is selectively etched relative to the liner. The liner is removed. The method may be repeated to a predetermined depth.

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming, on a substrate, a stack of alternating layers including a first layer of material and a second layer of material different from the first layer of material; forming a memory hole in the stack of alternating layers of the first layer of material and the second layer of material; depositing a layer of blocking oxide on sides defining the memory hole; depositing a layer of silicon atop the layer of blocking oxide to form a silicon channel; deposit core oxide to fill the silicon channel; removing the first layer of material to form spaces between the alternating layers of the second material; and one of depositing a third layer of material to partially fill the spaces to leave air gaps therein or depositing a fourth layer of material to fill the spaces.

Abstract: Methods of etching film stacks to from gaps of uniform width are described. A film stack is etched through a hardmask. A conformal liner is deposited in the gap. The bottom of the liner is removed. The film stack is selectively etched relative to the liner. The liner is removed. The method may be repeated to a predetermined depth.

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.

Abstract: Methods of manufacturing memory devices are provided. The methods decrease the thickness of the first layers and increase the thickness of the second layers. Semiconductor devices are described having a film stack comprising alternating nitride and second layers in a first portion of the device, the alternating nitride and second layers of the film stack having a nitride:oxide thickness ratio (Nf:Of); and a memory stack comprising alternating word line and second layers in a second portion of the device, the alternating word line and second layers of the memory stack having a word line:oxide thickness ratio (Wm:Om), wherein 0.1(Wm:Om)<Nf:Of<0.95(Wm:Om).

Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming, on a substrate, a stack of alternating layers including a first layer of material and a second layer of material different from the first layer of material; forming a memory hole in the stack of alternating layers of the first layer of material and the second layer of material; depositing a layer of blocking oxide on sides defining the memory hole; depositing a layer of silicon atop the layer of blocking oxide to form a silicon channel; deposit core oxide to fill the silicon channel; removing the first layer of material to form spaces between the alternating layers of the second material; and one of depositing a third layer of material to partially fill the spaces to leave air gaps therein or depositing a fourth layer of material to fill the spaces.

Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and an opening formed in the film stack, wherein the opening is filled with a metal dielectric layer, a multi-layer structure and a center filling layer, wherein the metal dielectric layer in the opening is interfaced with the conductive structure.

Abstract: A method of controlling polishing includes storing a base measurement, the base measurement being a measurement of a substrate after deposition of at least one layer overlying a semiconductor wafer and before deposition of an outer layer over the at least one layer, after deposition of the outer layer over the at least one layer and during polishing of the outer layer on substrate, receiving a sequence of raw measurements of the substrate from an in-situ monitoring system, normalizing each raw measurement in the sequence of raw measurement to generate a sequence of normalized measurements using the raw measurement and the base measurement, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on at least the sequence of normalized measurements.

Abstract: Methods of etching film stacks to from gaps of uniform width are described. A film stack is etched through a hardmask. A conformal liner is deposited in the gap. The bottom of the liner is removed. The film stack is selectively etched relative to the liner. The liner is removed. The method may be repeated to a predetermined depth.

Abstract: A buff module and method for using the same are provided. In one embodiment, a buff module includes housing having an interior volume, a plurality of drive rollers and a pair of buff heads. The drive rollers are arranged to rotate a substrate within the interior volume on a substantially horizontal axis. The buff heads are disposed in the housing, each buff head rotatable on an axis substantially aligned with the horizontal axis and movable to a position substantially parallel with the horizontal axis.

Abstract: A method of controlling polishing includes storing a base spectrum, the base spectrum being a spectrum of light reflected from a substrate after deposition of a deposited dielectric layers overlying a metallic layer or semiconductor wafer and before deposition of a non-metallic layer over the plurality of deposited dielectric layer. After deposition of the non-metallic layer and during polishing of the non-metallic layer on the substrate, measurements of a sequence of raw spectra of light reflected the substrate during polishing are received from an in-situ optical monitoring system. Each raw spectrum is normalized to generate a sequence of normalized spectra using the raw spectrum and the base spectrum. At least one of a polishing endpoint or an adjustment for a polishing rate is determined based on at least one normalized predetermined spectrum from the sequence of normalized spectra.

Abstract: A method of controlling polishing includes storing a base measurement, the base measurement being a measurement of a substrate after deposition of at least one layer overlying a semiconductor wafer and before deposition of an outer layer over the at least one layer, after deposition of the outer layer over the at least one layer and during polishing of the outer layer on substrate, receiving a sequence of raw measurements of the substrate from an in-situ monitoring system, normalizing each raw measurement in the sequence of raw measurement to generate a sequence of normalized measurements using the raw measurement and the base measurement, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on at least the sequence of normalized measurements.

Abstract: A method of controlling polishing includes storing a base measurement, the base measurement being an eddy current measurement of a substrate after deposition of at least one layer overlying a semiconductor wafer and before deposition of a conductive layer over the at least one layer, after deposition of the conductive layer over the at least one layer and during polishing of the conductive layer on substrate, receiving a sequence of raw measurements of the substrate from an in-situ eddy current monitoring system, normalizing each raw measurement in the sequence of raw measurement to generate a sequence of normalized measurements using the raw measurement and the base measurement, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on at least the sequence of normalized measurements.

Abstract: A method of controlling polishing includes storing a base measurement, the base measurement being an eddy current measurement of a substrate after deposition of at least one layer overlying a semiconductor wafer and before deposition of a conductive layer over the at least one layer, after deposition of the conductive layer over the at least one layer and during polishing of the conductive layer on substrate, receiving a sequence of raw measurements of the substrate from an in-situ eddy current monitoring system, normalizing each raw measurement in the sequence of raw measurement to generate a sequence of normalized measurements using the raw measurement and the base measurement, and determining at least one of a polishing endpoint or an adjustment for a polishing rate based on at least the sequence of normalized measurements.

Abstract: A method of controlling polishing includes storing a base spectrum, the base spectrum being a spectrum of light reflected from a substrate after deposition of a deposited dielectric layers overlying a metallic layer or semiconductor wafer and before deposition of a non-metallic layer over the plurality of deposited dielectric layer. After deposition of the non-metallic layer and during polishing of the non-metallic layer on the substrate, measurements of a sequence of raw spectra of light reflected the substrate during polishing are received from an in-situ optical monitoring system. Each raw spectrum is normalized to generate a sequence of normalized spectra using the raw spectrum and the base spectrum. At least one of a polishing endpoint or an adjustment for a polishing rate is determined based on at least one normalized predetermined spectrum from the sequence of normalized spectra.

Abstract: Methods for chemical mechanical polishing (CMP) of semiconductor substrates, and more particularly to temperature control during such chemical mechanical polishing are provided. In one aspect, the method comprises polishing the substrate with a polishing surface during a polishing process to remove a portion of the conductive material, repeatedly monitoring a temperature of the polishing surface during the polishing process, and exposing the polishing surface to a rate quench process in response to the monitored temperature so as to achieve a target value for the monitored temperature during the polishing process.