Abstract: A method of manufacturing a semiconductor element includes forming a mask on a front surface of a substrate, the mask having an opening to expose the front surface; growing a first semiconductor layer by epitaxially growing a semiconductor along the mask, starting from the front surface exposed through the opening, and growing a second semiconductor layer on a surface of the first semiconductor layer located opposite to the substrate in a layering direction, and providing an electrode on a surface of the second semiconductor layer located opposite to the surface of the first semiconductor layer in the layering direction. A width from an end portion of the surface to the electrode is smaller than a width of the mask.

Abstract: A manufacturing method for a semiconductor element includes a step of forming a mask partly having an opening and configured to cover a surface of a base substrate, and a step of forming a semiconductor layer containing a predetermined semiconductor material by inducing epitaxial growth along the mask from the surface of the base substrate exposed from an opening. A surface on the side closer to the semiconductor layer in the mask is formed of an amorphous first material that does not contain an element to serve as a donor or an acceptor in the predetermined semiconductor material.

Abstract: A method for manufacturing a semiconductor element includes providing, on a surface of a substrate 11, a mask 12 which has an opening 12a and in which a peripheral upper surface region of the opening is processed to have a predetermined structure, and epitaxially growing a semiconductor from the surface of the substrate exposed from the opening to the top of the peripheral upper surface region to fabricate a semiconductor element having a semiconductor layer 13 with the predetermined structure transferred thereon. In one example, the predetermined structure is due to a shape having a difference in level. In another example, the predetermined structure is due to a selectively arranged element, and the transferred element moves into the semiconductor layer.

Abstract: In this semiconductor device, a trench is formed on the upper surface of an n-type semiconductor layer laminated on a semiconductor substrate, a Schottky junction with metal is formed on the upper surface of an n-type region forming one side surface of the trench, and a pn junction is formed on the upper surface of an n-type region forming the other side surface of the trench. The pn junction is formed by a junction between the n-type region and the p-type semiconductor layer crystal-grown via epitaxial growth on the upper surface of the n-type region forming the other side surface.

Abstract: A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The memory cell array is configured to include a plurality of memory cells, and the word line decoder is configured to control selection and a voltage level of a word line connected to each of the memory cells. The time determination signal generation circuit is configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined, and the timing circuit is configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged.

Abstract: A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of “1”s in each of the rows is an even number.

Abstract: A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The memory cell array is configured to include a plurality of memory cells, and the word line decoder is configured to control selection and a voltage level of a word line connected to each of the memory cells. The time determination signal generation circuit is configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined, and the timing circuit is configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged.

Abstract: A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of “1”s in each of the rows is an even number.

Abstract: A semiconductor memory that includes a memory cell array by which power consumption can be reduced and that enables a reduction in circuit area. In the memory cell array, each of capacitor plate lines is arranged so as to connect with ferroelectric memory cells in a same row, and each of word lines is arranged so as to connect with ferroelectric memory cells in different rows in a column direction. In addition, of drive circuits for driving the capacitor plate lines and the word lines, part of word line drive circuits (WL drive circuits) are arranged in the column direction. Therefore, it is possible to drive all of the word lines without using a dummy area. As a result, circuit area can be reduced.

Abstract: Multiple unit transistors each having the same gate length are arranged in a gate-lengthwise direction to form a group of unit transistors. At least one unit transistor included in the group of unit transistors is used as a part of a gate bias circuit and acts as unit transistor (102) that is used for the bias circuit, and all of or part of the other unit transistors are connected in parallel and used as amplifier (101).

Abstract: Multiple unit transistors each having the same gate length are arranged in a gate-lengthwise direction to form a group of unit transistors. At least one unit transistor included in the group of unit transistors is used as a part of a gate bias circuit and acts as unit transistor (102) that is used for the bias circuit, and all of or part of the other unit transistors are connected in parallel and used as amplifier (101).

Abstract: A semiconductor memory that includes a memory cell array by which power consumption can be reduced and that enables a reduction in circuit area. In the memory cell array, each of capacitor plate lines is arranged so as to connect with ferroelectric memory cells in a same row, and each of word lines is arranged so as to connect with ferroelectric memory cells in different rows in a column direction. In addition, of drive circuits for driving the capacitor plate lines and the word lines, part of word line drive circuits (WL drive circuits) are arranged in the column direction. Therefore, it is possible to drive all of the word lines without using a dummy area. As a result, circuit area can be reduced.

Abstract: A bit line is connected, via a first pMOS transistor, to a first node whose potential is set at a prescribed negative voltage in advance. The gate voltage of the first pMOS transistor is set at a constant voltage that is slightly lower than its threshold voltage. During a read operation, a current that flows into the bit line from a memory cell in accordance with a residual dielectric polarization value of a ferroelectric capacitor always leaks to the first node, whereby the potential of the first node increases. The logical value of data stored in the memory cell is judged on the basis of a voltage increase at the first node. Since no control circuit for keeping the potential of the first node at the ground potential during a read operation is necessary, the layout size and the power consumption of a ferroelectric memory can be decreased.

Abstract: A bit line is connected, via a first pMOS transistor, to a first node whose potential is set at a prescribed negative voltage in advance. The gate voltage of the first pMOS transistor is set at a constant voltage that is slightly lower than its threshold voltage. During a read operation, a current that flows into the bit line from a memory cell in accordance with a residual dielectric polarization value of a ferroelectric capacitor always leaks to the first node, whereby the potential of the first node increases. The logical value of data stored in the memory cell is judged on the basis of a voltage increase at the first node. Since no control circuit for keeping the potential of the first node at the ground potential during a read operation is necessary, the layout size and the power consumption of a ferroelectric memory can be decreased.

Abstract: A base bias circuit (1) operates like a constant voltage source, and a base bias voltage generated thereby varies according to fluctuation of the environment temperature without being influenced by the supply voltage, to hold a collector bias voltage constant. The base bias circuit (1) has a function of controlling the base bias voltage according to a control signal coming from the outside. By using a resistor (6) and resistor (14) having suitable resistances, the bipolar transistors constituting the bias circuit (1) can be small in size to reduce the electric current consumed by the bias circuit (1) thereby to make unnecessary the RF choke inductor between a power transistor (13) and the bias circuit (1). In short, the cost is lowered by making the chip size small and by reducing the number of external parts.

Abstract: A base bias circuit (1) operates like a constant voltage source, and a base bias voltage generated thereby varies according to fluctuation of the environment temperature without being influenced by the supply voltage, to hold a collector bias voltage constant. The base bias circuit (1) has a function of controlling the base bias voltage according to a control signal coming from the outside. By using a resistor (6) and resistor (14) having suitable resistances, the bipolar transistors constituting the bias circuit (1) can be small in size to reduce the electric current consumed by the bias circuit (1) thereby to make unnecessary the RF choke inductor between a power transistor (13) and the bias circuit (1). In short, the cost is lowered by making the chip size small and by reducing the number of external parts.

Abstract: An analog amplifier circuit having an amplifier, an input matching circuit thereof and an output matching circuit thereof, said input matching circuit and said output matching circuit comprising: a circuit portion which capacitively functions with respect to a first frequency while inductively functions with respect to a second frequency, so as to match with respect to both of said first frequency and second frequency.