Patents by Inventor Tomohito KUDO
Tomohito KUDO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11869773Abstract: An object of the present invention is to improve the flatness of a surface electrode without increasing the number of steps in a semiconductor device having gate structures. A method of manufacturing a semiconductor device of the present invention includes the steps of discretely forming a plurality of gate structures on a first main surface of the semiconductor substrate, discretely forming a plurality of gate interlayer films covering the plurality of gate structures of the semiconductor substrate, forming a first surface electrode being thicker than the gate interlayer films on the first main surface of the semiconductor substrate between the plurality of the gate interlayer films and on the plurality of the gate interlayer films by sputtering, and removing convex portions of concave portions and the convex portions on the first surface electrode by dry etching using photolithography, to flatten an upper surface of the first surface electrode.Type: GrantFiled: October 18, 2021Date of Patent: January 9, 2024Assignee: Mitsubishi Electric CorporationInventor: Tomohito Kudo
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Publication number: 20230268429Abstract: A semiconductor substrate (1) includes a main region (2) and a sense region (3) having a smaller operation region area than that of the main region (2). An IGBT is formed in the main region (2). A MOSFET is formed as a sense device in the sense region (3) and has a gate electrode (15) connected to a gate electrode (15) of the IGBT. A front surface electrode (5) is formed on a front surface of the semiconductor substrate (1) in the main region (2). A rear surface electrode (20) is formed on a rear surface of the semiconductor substrate (1) in the main region (2) and the sense region (3). A current detection electrode (6) is formed on the front surface in the sense region (3) and separated from the front surface electrode (5).Type: ApplicationFiled: February 9, 2021Publication date: August 24, 2023Applicant: Mitsubishi Electric CorporationInventor: Tomohito KUDO
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Publication number: 20230207707Abstract: A silicon substrate has first to fourth semiconductor regions. The third semiconductor region is separated from the first semiconductor region of a first conductivity type by the second semiconductor region of a second conductivity type. The fourth semiconductor region of the second conductivity type is separated from the second semiconductor region by the third semiconductor region. A first electrode is provided on a first surface. A barrier metal layer is provided on a first portion of a second surface. A second electrode is provided on the second surface, and is separated from the first portion of the second surface by the barrier metal layer. The second electrode includes an aluminum-silicon (Al—Si) layer in contact with a second portion of the second surface, and an Al layer separated from the second portion of the second surface by the Al—Si layer.Type: ApplicationFiled: July 16, 2020Publication date: June 29, 2023Applicant: Mitsubishi Electric CorporationInventors: Toshiki FUKASAWA, Tomohito KUDO, Hideki HARUGUCHI
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Patent number: 11251046Abstract: An object of the present invention is to improve the flatness of a surface electrode without increasing the number of steps in a semiconductor device having gate structures. A method of manufacturing a semiconductor device of the present invention includes the steps of discretely forming a plurality of gate structures on a first main surface of the semiconductor substrate, discretely forming a plurality of gate interlayer films covering the plurality of gate structures of the semiconductor substrate, forming a first surface electrode being thicker than the gate interlayer films on the first main surface of the semiconductor substrate between the plurality of the gate interlayer films and on the plurality of the gate interlayer films by sputtering, and removing convex portions of concave portions and the convex portions on the first surface electrode by dry etching using photolithography, to flatten an upper surface of the first surface electrode.Type: GrantFiled: February 2, 2018Date of Patent: February 15, 2022Assignee: Mitsubishi Electric CorporationInventor: Tomohito Kudo
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Publication number: 20220037159Abstract: An object of the present invention is to improve the flatness of a surface electrode without increasing the number of steps in a semiconductor device having gate structures. A method of manufacturing a semiconductor device of the present invention includes the steps of discretely forming a plurality of gate structures on a first main surface of the semiconductor substrate, discretely forming a plurality of gate interlayer films covering the plurality of gate structures of the semiconductor substrate, forming a first surface electrode being thicker than the gate interlayer films on the first main surface of the semiconductor substrate between the plurality of the gate interlayer films and on the plurality of the gate interlayer films by sputtering, and removing convex portions of concave portions and the convex portions on the first surface electrode by dry etching using photolithography, to flatten an upper surface of the first surface electrode.Type: ApplicationFiled: October 18, 2021Publication date: February 3, 2022Applicant: Mitsubishi Electric CorporationInventor: Tomohito KUDO
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Patent number: 11211251Abstract: An object of the present invention is to improve the flatness of a surface electrode without increasing the number of steps in a semiconductor device having gate structures. A method of manufacturing a semiconductor device of the present invention includes the steps of discretely forming a plurality of gate structures on a first main surface of the semiconductor substrate, discretely forming a plurality of gate interlayer films covering the plurality of gate structures of the semiconductor substrate, forming a first surface electrode being thicker than the gate interlayer films on the first main surface of the semiconductor substrate between the plurality of the gate interlayer films and on the plurality of the gate interlayer films by sputtering, and removing convex portions of concave portions and the convex portions on the first surface electrode by dry etching using photolithography, to flatten an upper surface of the first surface electrode.Type: GrantFiled: February 2, 2018Date of Patent: December 28, 2021Assignee: Mitsubishi Electric CorporationInventor: Tomohito Kudo
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Publication number: 20200279744Abstract: An object of the present invention is to improve the flatness of a surface electrode without increasing the number of steps in a semiconductor device having gate structures. A method of manufacturing a semiconductor device of the present invention includes the steps of discretely forming a plurality of gate structures on a first main surface of the semiconductor substrate, discretely forming a plurality of gate interlayer films covering the plurality of gate structures of the semiconductor substrate, forming a first surface electrode being thicker than the gate interlayer films on the first main surface of the semiconductor substrate between the plurality of the gate interlayer films and on the plurality of the gate interlayer films by sputtering, and removing convex portions of concave portions and the convex portions on the first surface electrode by dry etching using photolithography, to flatten an upper surface of the first surface electrode.Type: ApplicationFiled: February 2, 2018Publication date: September 3, 2020Applicant: Mitsubishi Electric CorporationInventor: Tomohito KUDO
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Patent number: 10355082Abstract: A third dummy trench (11) is orthogonal to the first and second dummy trenches (9,10) in the dummy cell region of a substrate end portion. An interlayer insulating film (13) insulates the p-type diffusion layer (3,4) in the dummy cell region of a substrate center portion situated between the first and second dummy trenches (9,10) from the emitter electrode (14). The third dummy trench (11) separates the p-type diffusion layer (3,4) in the dummy cell region of the substrate center portion from the p-type diffusion layer (3,4,15) in the dummy cell region of the substrate end portion connected to the emitter electrode (14). A p-type well layer (15) is provided deeper than the third dummy trench (11) in the substrate end portion. The third dummy trench (11) is provided closer to a center of the n-type substrate than the p-type well layer (15).Type: GrantFiled: August 19, 2015Date of Patent: July 16, 2019Assignee: Mitsubishi Electronic CorporationInventors: Tomohito Kudo, Yoshihumi Tomomatsu, Hideki Haruguchi, Yasuo Ata
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Publication number: 20180083101Abstract: A third dummy trench (11) is orthogonal to the first and second dummy trenches (9,10) in the dummy cell region of a substrate end portion. An interlayer insulating film (13) insulates the p-type diffusion layer (3,4) in the dummy cell region of a substrate center portion situated between the first and second dummy trenches (9,10) from the emitter electrode (14). The third dummy trench (11) separates the p-type diffusion layer (3,4) in the dummy cell region of the substrate center portion from the p-type diffusion layer (3,4,15) in the dummy cell region of the substrate end portion connected to the emitter electrode (14). A p-type well layer (15) is provided deeper than the third dummy trench (11) in the substrate end portion. The third dummy trench (11) is provided closer to a center of the n-type substrate than the p-type well layer (15).Type: ApplicationFiled: August 19, 2015Publication date: March 22, 2018Applicant: Mitsubishi Electric CorporationInventors: Tomohito KUDO, Yoshihumi TOMOMATSU, Hideki HARUGUCHI, Yasuo ATA