Patents by Inventor Tomoko Kinoshita

Tomoko Kinoshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11121247
    Abstract: A semiconductor device includes a semiconductor portion, a first insulating film, a second insulating film, a first contact, a second contact, and a gate electrode. The first insulating film is provided on the semiconductor portion. The second insulating film is contacting the first insulating film, is provided on the semiconductor portion, and is thicker than the first insulating film. A through-hole is formed in the second insulating film. The first contact has a lower end connected to the semiconductor portion. The second contact has a lower portion disposed inside the through-hole and a lower end connected to the semiconductor portion. The gate electrode is positioned between the first contact and the second contact, is provided on the first insulating film, and is provided on a portion of the second insulating film other than the through-hole.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: September 14, 2021
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Tomoko Kinoshita, Daisuke Shinohara, Kanako Komatsu, Yoshiaki Ishii, Sudharsan Sundaram Prabhakaran
  • Publication number: 20200303537
    Abstract: A semiconductor device includes a semiconductor portion, a first insulating film, a second insulating film, a first contact, a second contact, and a gate electrode. The first insulating film is provided on the semiconductor portion. The second insulating film is contacting the first insulating film, is provided on the semiconductor portion, and is thicker than the first insulating film. A through-hole is formed in the second insulating film. The first contact has a lower end connected to the semiconductor portion. The second contact has a lower portion disposed inside the through-hole and a lower end connected to the semiconductor portion. The gate electrode is positioned between the first contact and the second contact, is provided on the first insulating film, and is provided on a portion of the second insulating film other than the through-hole.
    Type: Application
    Filed: September 16, 2019
    Publication date: September 24, 2020
    Inventors: Tomoko Kinoshita, Daisuke Shinohara, Kanako Komatsu, Yoshiaki Ishii, Sudharsan Sundaram Prabhakaran
  • Publication number: 20200091304
    Abstract: A semiconductor device includes a semiconductor portion of a first conductivity type, an insulating portion provided in an upper layer portion of the semiconductor portion, a source region, a drain region and a gate electrode. The insulating portion surrounds an active area. The source region and the drain region are provided inside the active area and separated from each other along a first direction parallel to an upper surface of the semiconductor portion. The source region and the drain region are of a second conductivity type. The gate electrode is provided above the semiconductor portion. The gate electrode is disposed in a region directly above a region between the source region and the drain region, and disposed in a region directly above an end portion in a second direction of the active area. The second direction is orthogonal to the first direction.
    Type: Application
    Filed: February 26, 2019
    Publication date: March 19, 2020
    Inventors: Mariko Yamashita, Tomoko Kinoshita, Keita Takahashi, Kanako Komatsu
  • Patent number: 6914789
    Abstract: A switching power supply apparatus is provided, wherein an optimal blanking interval can be obtained for an entire load range. The switching power supply apparatus is configured such that an on-blanking pulse signal generating circuit 31 generates a blanking pulse signal based on an error voltage signal VEAO, and sets a blanking interval that corresponds to the load condition. For example, the reference voltage and the voltage value of the error voltage signal VEAO are compared and the blanking pulse signal that shortens the blanking interval is generated during a light load, that is, when the voltage value of the error voltage signal VEAO is less than or equal to the reference voltage.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: July 5, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tomoko Kinoshita, Yoshihiro Mori
  • Publication number: 20040136206
    Abstract: A switching power supply apparatus is provided, wherein an optimal blanking interval can be obtained for an entire load range. The switching power supply apparatus is configured such that an on-blanking pulse signal generating circuit 31 generates a blanking pulse signal based on an error voltage signal VEAO, and sets a blanking interval that corresponds to the load condition. For example, the reference voltage and the voltage value of the error voltage signal VEAO are compared and the blanking pulse signal that shortens the blanking interval is generated during a light load, that is, when the voltage value of the error voltage signal VEAO is less than or equal to the reference voltage.
    Type: Application
    Filed: December 22, 2003
    Publication date: July 15, 2004
    Applicant: Matsushita Elec Co., Ltd.
    Inventors: Tomoko Kinoshita, Yoshihiro Mori