Patents by Inventor Tomoko Sekiguchi
Tomoko Sekiguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9830524Abstract: In the present invention, at the time of measuring, using a CD-SEM, a length of a resist that shrinks when irradiated with an electron beam, in order to highly accurately estimate a shape and dimensions of the resist before shrink, a shrink database with respect to various patterns is previously prepared, said shrink database containing cross-sectional shape data obtained prior to electron beam irradiation, a cross-sectional shape data group and a CD-SEM image data group, which are obtained under various electron beam irradiation conditions, and models based on such data and data groups, and a CD-SEM image of a resist pattern to be measured is obtained (S102), then, the CD-SEM image and data in the shrink database are compared with each other (S103), and the shape and dimensions of the pattern before the shrink are estimated and outputted (S104).Type: GrantFiled: May 24, 2012Date of Patent: November 28, 2017Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATIONInventors: Tomoko Sekiguchi, Takeyoshi Ohashi, Junichi Tanaka, Zhaohui Cheng, Ruriko Tsuneta, Hiroki Kawada, Seiko Hitomi
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Patent number: 9305744Abstract: The objective of the invention is to provide a measuring method that can determine pattern contours and dimensions with high precision even if an object to be measured shrinks due to electron beam radiations. In order to achieve this objective, a method, which performs measurements by irradiating an electron beam onto a sample having a pattern formed on a primary coating thereof, prepares an SEM image and contour of the pattern (S201, S202), material parameters of the pattern part and primary coating part of the sample (S203, S204), and a beam condition in irradiating the electron beam onto the sample (S205), and uses these prepared things to calculate a pattern shape or dimensions before the irradiation of the electron beam (S206).Type: GrantFiled: September 27, 2012Date of Patent: April 5, 2016Assignee: Hitachi High-Technologies CorporationInventors: Takeyoshi Ohashi, Junichi Tanaka, Tomoko Sekiguchi, Hiroki Kawada
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Publication number: 20150036914Abstract: In the present invention, at the time of measuring, using a CD-SEM, a length of a resist that shrinks when irradiated with an electron beam, in order to highly accurately estimate a shape and dimensions of the resist before shrink, a shrink database with respect to various patterns is previously prepared, said shrink database containing cross-sectional shape data obtained prior to electron beam irradiation, a cross-sectional shape data group and a CD-SEM image data group, which are obtained under various electron beam irradiation conditions, and models based on such data and data groups, and a CD-SEM image of a resist pattern to be measured is obtained (S102), then, the CD-SEM image and data in the shrink database are compared with each other (S103), and the shape and dimensions of the pattern before the shrink are estimated and outputted (S104).Type: ApplicationFiled: May 24, 2012Publication date: February 5, 2015Inventors: Tomoko Sekiguchi, Takeyoshi Ohashi, Junichi Tanaka, Zhaohui Cheng, Ruriko Tsuneta, Hiroki Kawada, Seiko Hitomi
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Publication number: 20140246585Abstract: The objective of the invention is to provide a measuring method that can determine pattern contours and dimensions with high precision even if an object to be measured shrinks due to electron beam radiations. In order to achieve this objective, a method, which performs measurements by irradiating an electron beam onto a sample having a pattern formed on a primary coating thereof, prepares an SEM image and contour of the pattern (S201, S202), material parameters of the pattern part and primary coating part of the sample (S203, S204), and a beam condition in irradiating the electron beam onto the sample (S205), and uses these prepared things to calculate a pattern shape or dimensions before the irradiation of the electron beam (S206).Type: ApplicationFiled: September 27, 2012Publication date: September 4, 2014Applicant: Hitachi High-Technologies CorporationInventors: Takeyoshi Ohashi, Junichi Tanaka, Tomoko Sekiguchi, Hiroki Kawada
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Patent number: 8790948Abstract: In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mm2 or more and 28.8 J/mm2 or less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.Type: GrantFiled: November 23, 2011Date of Patent: July 29, 2014Assignee: Hitachi, Ltd.Inventors: Keiji Watanabe, Toshiyuki Mine, Akio Shima, Tomoko Sekiguchi, Ryuta Tsuchiya
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Publication number: 20130083193Abstract: According to one embodiment, an electronic apparatus includes: an imaging module configured to take an image; a display configured to display information; a detector configured to detect an electrical device from the image taken by the imaging module, wherein the electrical device is configured to consume power; and a display controller configured to control the display to display first information indicative of power consumption of the electrical device and second information, the second information dependent on a type of the electrical device, for evaluating an operation influencing the power consumption of the electrical device.Type: ApplicationFiled: August 3, 2012Publication date: April 4, 2013Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Takehiko OKUYAMA, Masashige YOGO, Tomoko SEKIGUCHI
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Publication number: 20120149143Abstract: In the existent method for manufacturing a solar cell, manufacture of a solar cell having a quantum well having a crystalline well layer and capable of controlling the thickness of the well layer was difficult. A quantum well having an amorphous well layer, comprising a barrier layer and an amorphous well layer is formed and then the quantum well having the amorphous well layer is annealed thereby crystallizing the amorphous well layer to form a quantum well having a crystalline well layer. By applying energy density applied to the amorphous well layer at an energy density of 1.26 J/mm2 or more and 28.8 J/mm2 or less, the crystalline well layer can be formed and the lamination structure of the quantum well can be maintained simultaneously.Type: ApplicationFiled: November 23, 2011Publication date: June 14, 2012Applicant: Hitachi, Ltd.Inventors: Keiji WATANABE, Toshiyuki MINE, Akio SHIMA, Tomoko SEKIGUCHI, Ryuta TSUCHIYA
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Publication number: 20090230510Abstract: A rutile phase can be formed even in the case of a thin film by adding nickel or cobalt to titanium dioxide in the range of 0.5 to 10 atm %, and the use of this element-added titanium dioxide film in a capacitor dielectric film results in an increase in capacitance per unit area of a DRAM memory cell and enables a high-integration DRAM to be realized at low cost.Type: ApplicationFiled: March 9, 2009Publication date: September 17, 2009Applicant: Elpida Memory, Inc.Inventors: Hiroshi Miki, Tomoko Sekiguchi, Naomi Inada, Mitsuhiro Horikawa
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Publication number: 20080157157Abstract: A DRAM capacitor uses ruthenium or ruthenium oxide as an upper electrode and hafnium dioxide or zirconium oxide as an insulation layer. The DRAM capacitor is intended to suppress diffusion of ruthenium, etc. into hafnium dioxide. Tantalum pentoxide or niobium oxide having a higher permittivity than that of the insulation layer is inserted as a cap insulation layer to the boundary between the upper electrode of ruthenium or ruthenium oxide and the insulation layer of hafnium dioxide or zirconium oxide to thereby suppress diffusion of ruthenium, etc. into hafnium dioxide, etc.Type: ApplicationFiled: November 15, 2007Publication date: July 3, 2008Inventors: Osamu TONOMURA, Hiroshi MIKI, Tomoko SEKIGUCHI, Kenichi TAKEDA
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Patent number: 7364965Abstract: A semiconductor device having a DRAM has a capacitor in which a dielectric film and an upper electrode are laminated on a lower electrode comprising a polysilicone, in which a natural oxide film oxidized by oxygen in the atmosphere grows to at least 1.5 nm on the surface of a lower electrode of the capacitor. Further, in forming the dielectric film, the dioxide film further grows in the case of using an oxidative raw material. This brings forth a reduction in capacitance, and an increase of a leakage current is caused. Therefore, after a dielectric film having a reduction property has been formed, the reduction property is promoted by a heat treatment to thereby reduce a dioxide film and realize making the dioxide film on the lower electrode surface thinner.Type: GrantFiled: November 12, 2004Date of Patent: April 29, 2008Assignee: Hitachi, Ltd.Inventors: Osamu Tonomura, Hiroshi Miki, Yuichi Matsui, Tomoko Sekiguchi, Kikuo Watanabe
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Patent number: 7247890Abstract: Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.Type: GrantFiled: September 1, 2004Date of Patent: July 24, 2007Assignee: Hitachi, Ltd.Inventors: Tomoko Sekiguchi, Shinichiro Kimura, Renichi Yamada, Kikuo Watanabe, Hiroshi Miki, Kenichi Takeda
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Publication number: 20050142742Abstract: A semiconductor device having a DRAM has a capacitor in which a dielectric film and an upper electrode are laminated on a lower electrode comprising a polysilicone, in which a natural oxide film oxidized by oxygen in the atmosphere grows to at least 1.5 nm on the surface of a lower electrode of the capacitor. Further, in forming the dielectric film, the dioxide film further grows in the case of using an oxidative raw material. This brings forth a reduction in capacitance, and an increase of a leakage current is caused. Therefore, after a dielectric film having a reduction property has been formed, the reduction property is promoted by a heat treatment to thereby reduce a dioxide film and realize making the dioxide film on the lower electrode surface thinner.Type: ApplicationFiled: November 12, 2004Publication date: June 30, 2005Inventors: Osamu Tonomura, Hiroshi Miki, Yuichi Matsui, Tomoko Sekiguchi, Kikuo Watanabe
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Publication number: 20050098813Abstract: Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.Type: ApplicationFiled: September 1, 2004Publication date: May 12, 2005Inventors: Tomoko Sekiguchi, Shinichiro Kimura, Renichi Yamada, Kikuo Watanabe, Hiroshi Miki, Kenichi Takeda
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Patent number: 6150657Abstract: An energy filter has a plurality of deflection means and is constructed by using the plural deflection means so that an average track of an electron beam is symmetric and the normal line to a symmetric plane is inclined against an incident direction of the electron beam.Type: GrantFiled: August 25, 1998Date of Patent: November 21, 2000Assignee: Hitachi, Ltd.Inventors: Koji Kimoto, Yoshifumi Taniguchi, Shunroku Taya, Shigeto Isakozawa, Takashi Aoyama, Masakazu Saito, Tomoko Sekiguchi