Patents by Inventor Tomonobu Tsuchiya

Tomonobu Tsuchiya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11114817
    Abstract: Disclosed herein is a semiconductor laser device utilizing a sub-mount substrate that is capable of having a further sufficient heat dissipation property. The semiconductor laser device comprises: a monocrystalline sub-mount substrate having a crystalline structure including a first crystalline plane (c-plane) having a normal line direction on a first crystalline axis (c-axis) and a second crystalline plane (a-plane) having a normal line direction on a second crystalline axis (a-axis) having a higher thermal conductivity than the first crystalline axis; and a semiconductor laser chip configured to be joined to a side of a first surface of the sub-mount substrate. The first crystalline plane inclines with respect to the first surface of the sub-mount substrate.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: September 7, 2021
    Assignee: USHIO DENKI KABUSHIKI KAISHA
    Inventors: Masato Hagimoto, Hironori Yanagisawa, Tomonobu Tsuchiya
  • Patent number: 11062892
    Abstract: The objective of the present invention is to provide a charged particle detector and a charged particle beam device with which it is possible to acquire a high luminous output while rapidly eliminating charged particles that are incident to a scintillator. In order to achieve said objective the present invention proposes: a charged particle detector provided with a light-emitting unit including a laminated structure obtained by laminating a GaInN-containing layer and a GaN layer, and provided with a conductive layer that is in contact with the GaInN-containing layer on the charged particle incidence surface side of the laminated structure; and a charged particle beam device.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: July 13, 2021
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Shin Imamura, Takashi Ohshima, Tomonobu Tsuchiya, Hajime Kawano, Makoto Suzuki
  • Patent number: 10984979
    Abstract: The disclosure provides a charged particle detector including a scintillator that emits light with stable intensity and obtains high light emission intensity regardless of an energy of an incident electron. The disclosure provides the charged particle detector including: a first light-emitting part (21) in which a layer containing Ga1-x-yAlxInyN (where 0?x<1, 0?y<1) and a layer containing GaN are alternately laminated; a second light-emitting part (23) in which the layer containing Ga1-x-yAlxInyN (where 0?x<1, 0?y<1) and the layer containing GaN are alternately laminated; and a non-light-emitting part (22) that is interposed between the first light-emitting part (21) and the second light-emitting part (23) (see FIG. 2).
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: April 20, 2021
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventors: Shin Imamura, Takashi Ohshima, Tomonobu Tsuchiya, Hajime Kawano, Shahedul Hoque, Shunsuke Mizutani, Makoto Suzuki
  • Patent number: 10840671
    Abstract: Disclosed herein is a semiconductor laser device utilizing a monocrystalline SiC substrate that is capable of assuring a sufficient heat dissipation property. The semiconductor laser device comprises: a monocrystalline SiC substrate having an electrical conductivity, the substrate having a first surface and a second surface; and a semiconductor laser chip (LD chip) arranged on the first surface. Also, the semiconductor laser device may comprise an insulating film arranged at a side of the first surface of the SiC substrate and configured to insulate a first electric conductive layer onto which the semiconductor laser chip is mounted and an electric conductive member (a second electric conductive layer and a heatsink portion) to be joined to a side of the second surface of the SiC substrate.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: November 17, 2020
    Assignee: USHIO DENKI KABUSHIKI KAISHA
    Inventors: Masato Hagimoto, Susumu Sorimachi, Tomonobu Tsuchiya
  • Publication number: 20190355549
    Abstract: The disclosure provides a charged particle detector including a scintillator that emits light with stable intensity and obtains high light emission intensity regardless of an energy of an incident electron. The disclosure provides the charged particle detector including: a first light-emitting part (21) in which a layer containing Ga1-x-yAlxInyN (where 0?x<1, 0?y<1) and a layer containing GaN are alternately laminated; a second light-emitting part (23) in which the layer containing Ga1-x-yAlxInyN (where 0?x<1, 0?y<1) and the layer containing GaN are alternately laminated; and a non-light-emitting part (22) that is interposed between the first light-emitting part (21) and the second light-emitting part (23) (see FIG. 2).
    Type: Application
    Filed: January 25, 2018
    Publication date: November 21, 2019
    Inventors: Shin IMAMURA, Takashi OHSHIMA, Tomonobu TSUCHIYA, Hajime KAWANO, Shahedul HOQUE, Shunsuke MIZUTANI, Makoto SUZUKI
  • Publication number: 20190027351
    Abstract: The objective of the present invention is to provide a charged particle detector and a charged particle beam device with which it is possible to acquire a high luminous output while rapidly eliminating charged particles that are incident to a scintillator. In order to achieve said objective the present invention proposes: a charged particle detector provided with a light-emitting unit including a laminated structure obtained by laminating a GaInN-containing layer and a GaN layer, and provided with a conductive layer that is in contact with the GaInN-containing layer on the charged particle incidence surface side of the laminated structure; and a charged particle beam device.
    Type: Application
    Filed: January 25, 2017
    Publication date: January 24, 2019
    Applicant: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Shin IMAMURA, Takashi OHSHIMA, Tomonobu TSUCHIYA, Hajime KAWANO, Makoto SUZUKI
  • Publication number: 20180278016
    Abstract: Disclosed herein is a semiconductor laser device utilizing a sub-mount substrate that is capable of having a further sufficient heat dissipation property. The semiconductor laser device comprises: a monocrystalline sub-mount substrate having a crystalline structure including a first crystalline plane (c-plane) having a normal line direction on a first crystalline axis (c-axis) and a second crystalline plane (a-plane) having a normal line direction on a second crystalline axis (a-axis) having a higher thermal conductivity than the first crystalline axis; and a semiconductor laser chip configured to be joined to a side of a first surface of the sub-mount substrate. The first crystalline plane inclines with respect to the first surface of the sub-mount substrate.
    Type: Application
    Filed: March 26, 2018
    Publication date: September 27, 2018
    Applicant: USHIO OPTO SEMICONDUCTORS, INC.
    Inventors: Masato HAGIMOTO, Hironori YANAGISAWA, Tomonobu TSUCHIYA
  • Publication number: 20180278015
    Abstract: Disclosed herein is a semiconductor laser device utilizing a monocrystalline SiC substrate that is capable of assuring a sufficient heat dissipation property. The semiconductor laser device comprises: a monocrystalline SiC substrate having an electrical conductivity, the substrate having a first surface and a second surface; and a semiconductor laser chip (LD chip) arranged on the first surface. Also, the semiconductor laser device may comprise an insulating film arranged at a side of the first surface of the SiC substrate and configured to insulate a first electric conductive layer onto which the semiconductor laser chip is mounted and an electric conductive member (a second electric conductive layer and a heatsink portion) to be joined to a side of the second surface of the SiC substrate.
    Type: Application
    Filed: March 26, 2018
    Publication date: September 27, 2018
    Applicant: USHIO OPTO SEMICONDUCTORS, INC.
    Inventors: Masato HAGIMOTO, Susumu SORIMACHI, Tomonobu TSUCHIYA
  • Patent number: 9530858
    Abstract: Disclosed are an npn-type bipolar transistor as a nitride semiconductor device having good characteristics, and a method of manufacturing the same. A so-called pn epitaxial substrate has a structure wherein an n-type collector layer and a p-type base layer of a three-layer structure are provided over a substrate. The three-layer structure includes first (lower layer side), second, and third (upper layer side) p-type base layers which differ in thickness and p-type impurity concentration. In a partial region inside the second p-type base layer located as an intermediate layer in the p-type base layer of the three-layer structure, an n-type emitter region is formed by ion implantation.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: December 27, 2016
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Akihisa Terano, Tomonobu Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima
  • Publication number: 20160013327
    Abstract: To provide a nitride semiconductor diode that includes conductive layers formed with a two-dimensional electron gas and achieves low on-state resistance characteristics, a high withstand voltage, and low reverse leakage current characteristics, each of the AlGaN layers and the GaN layers in a nitride semiconductor diode including conductive layers of a two-dimensional electron gas that are formed when the AlGaN layers and the GaN layers are alternately stacked has a double-layer structure formed with an undoped layer (upper layer) and an n-type layer (lower layer).
    Type: Application
    Filed: March 8, 2013
    Publication date: January 14, 2016
    Inventors: Akihisa TERANO, Tomonobu TSUCHIYA, Tsukuru OHTOSHI
  • Publication number: 20150179780
    Abstract: Disclosed are an npn-type bipolar transistor as a nitride semiconductor device having good characteristics, and a method of manufacturing the same. A so-called pn epitaxial substrate has a structure wherein an n-type collector layer and a p-type base layer of a three-layer structure are provided over a substrate. The three-layer structure includes first (lower layer side), second, and third (upper layer side) p-type base layers which differ in thickness and p-type impurity concentration. In a partial region inside the second p-type base layer located as an intermediate layer in the p-type base layer of the three-layer structure, an n-type emitter region is formed by ion implantation.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 25, 2015
    Inventors: Akihisa TERANO, Tomonobu TSUCHIYA, Naoki KANEDA, Tomoyoshi MISHIMA
  • Patent number: 9059328
    Abstract: A nitride semiconductor element having a high reverse breakdown voltage and a method of manufacturing the same are provided. A diode (a vertical-type SBD) has an n?-type nitride semiconductor layer (a drift region) formed on an n-type nitride semiconductor substrate, a p-type nitride semiconductor layer formed on the n?-type nitride semiconductor layer, and besides, an anode electrode formed on the p-type nitride semiconductor layer. The p-type nitride semiconductor layer has a relatively-thin first portion and a relatively-thick second portion provided so as to surround the first portion as being in contact with an outer circumference of the first portion. Also, the relatively-thin first portion of the p-type nitride semiconductor layer is formed thinner than the second portion so as to be depleted. The relatively-thick second portion of the p-type nitride semiconductor layer forms a guard ring part.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: June 16, 2015
    Assignee: Hitachi Metals, Ltd.
    Inventors: Akihisa Terano, Kazuhiro Mochizuki, Tomonobu Tsuchiya, Tadayoshi Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima
  • Patent number: 8896027
    Abstract: Disclosed is a high performance nitride semiconductor having a reverse leak current characteristic with two-dimensional electron gas as a conductive layer. A desired impurity is diffused into or a nitride semiconductor to which a desired impurity is added is re-grown on the bottom surface and the side face portion of a recessed portion formed by dry etching using chlorine gas on the upper surface of a nitride semiconductor stacked film to increase resistance of the side face portion of the nitride semiconductor stacked film contacting an anode electrode, reducing the reverse leak current.
    Type: Grant
    Filed: November 24, 2012
    Date of Patent: November 25, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Akihisa Terano, Kazuhiro Mochizuki, Tomonobu Tsuchiya
  • Publication number: 20140117376
    Abstract: A nitride semiconductor element having a high reverse breakdown voltage and a method of manufacturing the same are provided. A diode (a vertical-type SBD) has an n?-type nitride semiconductor layer (a drift region) formed on an n-type nitride semiconductor substrate, a p-type nitride semiconductor layer formed on the n?-type nitride semiconductor layer, and besides, an anode electrode formed on the p-type nitride semiconductor layer. The p-type nitride semiconductor layer has a relatively-thin first portion and a relatively-thick second portion provided so as to surround the first portion as being in contact with an outer circumference of the first portion. Also, the relatively-thin first portion of the p-type nitride semiconductor layer is formed thinner than the second portion so as to be depleted. The relatively-thick second portion of the p-type nitride semiconductor layer forms a guard ring part.
    Type: Application
    Filed: October 29, 2013
    Publication date: May 1, 2014
    Applicant: Hitachi Metals, Ltd.
    Inventors: Akihisa TERANO, Kazuhiro MOCHIZUKI, Tomonobu TSUCHIYA, Tadayoshi TSUCHIYA, Naoki KANEDA, Tomoyoshi MISHIMA
  • Patent number: 8598594
    Abstract: In a semiconductor device including a stack structure having heterojunction units formed by alternately stacking GaN (gallium nitride) films and barrier films which are different in forbidden band width, a first electrode formed in a Schottky barrier contact with one sidewall of the stack structure, and a second electrode formed in contact with the other sidewall, an oxide film is interposed between the first electrode and the barrier films. Therefore, the reverse leakage current is prevented from flowing through defects remaining in the barrier films due to processing of the barrier films, so that a reverse leakage current of a Schottky barrier diode is reduced.
    Type: Grant
    Filed: February 4, 2012
    Date of Patent: December 3, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Kazuhiro Mochizuki, Takashi Ishigaki, Akihisa Terano, Tomonobu Tsuchiya
  • Publication number: 20120228626
    Abstract: In a semiconductor device including a stack structure having heterojunction units formed by alternately stacking GaN (gallium nitride) films and barrier films which are different in forbidden band width, a first electrode formed in a Schottky barrier contact with one sidewall of the stack structure, and a second electrode formed in contact with the other sidewall, an oxide film is interposed between the first electrode and the barrier films. Therefore, the reverse leakage current is prevented from flowing through defects remaining in the barrier films due to processing of the barrier films, so that a reverse leakage current of a Schottky barrier diode is reduced.
    Type: Application
    Filed: February 4, 2012
    Publication date: September 13, 2012
    Inventors: Kazuhiro Mochizuki, Takashi Ishigaki, Akihisa Terano, Tomonobu Tsuchiya
  • Patent number: 8124432
    Abstract: In an InGaN-based nitride semiconductor optical device having a long wavelength (440 nm or more) equal to or more than that of blue, the increase of a wavelength is realized while suppressing In (Indium) segregation and deterioration of crystallinity. In the manufacture of an InGaN-based nitride semiconductor optical device having an InGaN-based quantum well active layer including an InGaN well layer and an InGaN barrier layer, a step of growing the InGaN barrier layer includes: a first step of adding hydrogen at 1% or more to a gas atmosphere composed of nitrogen and ammonia and growing a GaN layer in the gas atmosphere; and a second step of growing the InGaN barrier layer in a gas atmosphere composed of nitrogen and ammonia.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: February 28, 2012
    Assignee: Opnext Japan, Inc.
    Inventors: Tomonobu Tsuchiya, Shigehisa Tanaka, Akihisa Terano, Kouji Nakahara
  • Patent number: 8068526
    Abstract: A purpose is to provide a semiconductor optical device having good characteristics to be formed on a semi-insulating InP substrate. Firstly, a semi-insulating substrate including a Ru—InP layer on a conductive substrate is used. Secondly, a semi-insulating substrate including a Ru—InP layer on a Ru—InP substrate or an Fe—InP substrate is used and semiconductor layers of an n-type semiconductor layer, a quantum-well layer, and a p-type semiconductor layer are stacked in this order.
    Type: Grant
    Filed: December 1, 2009
    Date of Patent: November 29, 2011
    Assignee: Opnext Japan, Inc.
    Inventors: Shigeki Makino, Takeshi Kitatani, Tomonobu Tsuchiya
  • Patent number: 7822088
    Abstract: A nitride semiconductor light emitting device operating on a low voltage and excelling in reliability and performance is to be provided. It has a multi-layered p-type clad layer of at least two layers of a first p-type clad layer and a second p-type clad layer, wherein the second p-type clad layer contains a p-type impurity in a higher concentration the first p-type clad layer does, has a thickness ranging from 2 to 20 nm, and is formed of AlYGa1-YN whose Al content has a relationship of X?Y to the first p-type clad layer doped with a p-type impurity containing at least an AlXGa1-XN (0<X?0.2) layer, while a p-type ohmic electrode is formed at least over the second p-type clad layer in contact therewith.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: October 26, 2010
    Assignee: Opnext Japan, Inc.
    Inventors: Akihisa Terano, Tomonobu Tsuchiya
  • Publication number: 20100189154
    Abstract: A purpose is to provide a semiconductor optical device having good characteristics to be formed on a semi-insulating InP substrate. Firstly, a semi-insulating substrate including a Ru—InP layer on a conductive substrate is used. Secondly, a semi-insulating substrate including a Ru—InP layer on a Ru—InP substrate or an Fe—InP substrate is used and semiconductor layers of an n-type semiconductor layer, a quantum-well layer, and a p-type semiconductor layer are stacked in this order.
    Type: Application
    Filed: December 1, 2009
    Publication date: July 29, 2010
    Inventors: Shigeki Makino, Takeshi Kitatani, Tomonobu Tsuchiya