Patents by Inventor Tomonori Nishimura

Tomonori Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230345114
    Abstract: An electronic apparatus according to the present invention includes at least one memory and at least one processor which function as: a detection unit configured to detect a line-of-sight position of a user within a display region; and a display control unit configured to control such that a first indicator is displayed on a basis of the line-of-sight position detected by the detection unit and an item is displayed at a position that does not overlap a range indicated by the first indicator when a predetermined condition is satisfied and is within a predetermined range from the range in response to the predetermined condition being satisfied.
    Type: Application
    Filed: April 11, 2023
    Publication date: October 26, 2023
    Inventor: Tomonori NISHIMURA
  • Patent number: 10748776
    Abstract: In the present invention, a contact layer formed of a material having an electron concentration of less than 1×1022 cm?3 is directly provided on a surface of a semiconductor crystal having an n-type conductivity with a band gap of 1.2 eV or less at room temperature. Consequently, the wave function penetration from the contact layer side to the semiconductor surface side is reduced. As a result, the formation of the energy barrier height·?B due to the Fermi level pinning phenomenon is much suppressed. It is possible to achieve the contact with a lower resistivity and with high ohmic properties.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: August 18, 2020
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira Toriumi, Tomonori Nishimura
  • Publication number: 20190228978
    Abstract: In the present invention, a contact layer formed of a material having an electron concentration of less than 1×1022 cm?3 is directly provided on a surface of a semiconductor crystal having an n-type conductivity with a band gap of 1.2 eV or less at room temperature. Consequently, the wave function penetration from the contact layer side to the semiconductor surface side is reduced. As a result, the formation of the energy barrier height·?B due to the Fermi level pinning phenomenon is much suppressed. It is possible to achieve the contact with a lower resistivity and with high ohmic properties.
    Type: Application
    Filed: February 23, 2017
    Publication date: July 25, 2019
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira Toriumi, Tomonori Nishimura
  • Patent number: 10109710
    Abstract: A semiconductor device having a channel region that is formed in a germanium layer and has a first conductive type, and a source region and a drain region that are formed in the germanium layer and have a second conductive type different from the first conductive type, wherein an oxygen concentration in the channel region is less than an oxygen concentration in a junction interface between at least one of the source region and the drain region and a region that surrounds the at least one of the source region and the drain region and has the first conductive type.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: October 23, 2018
    Assignee: Japan Science and Technology Agency
    Inventors: Akira Toriumi, Choong-hyun Lee, Tomonori Nishimura
  • Publication number: 20170317170
    Abstract: A semiconductor device having a channel region that is formed in a germanium layer and has a first conductive type, and a source region and a drain region that are formed in the germanium layer and have a second conductive type different from the first conductive type, wherein an oxygen concentration in the channel region is less than an oxygen concentration in a junction interface between at least one of the source region and the drain region and a region that surrounds the at least one of the source region and the drain region and has the first conductive type.
    Type: Application
    Filed: November 2, 2015
    Publication date: November 2, 2017
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira TORIUMI, Choong-hyun LEE, Tomonori NISHIMURA
  • Patent number: 9722026
    Abstract: A semiconductor structure includes: a germanium layer; and a first insulating film that is formed on an upper surface of the germanium layer, primarily contains germanium oxide and a substance having an oxygen potential lower than an oxygen potential of germanium oxide, and has a physical film thickness of 3 nm or less; wherein a half width of frequency to height in a 1 ?m square area of the upper surface of the germanium layer is 0.7 nm or less.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: August 1, 2017
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira Toriumi, Toshiyuki Tabata, Choong Hyun Lee, Tomonori Nishimura, Cimang Lu
  • Patent number: 9647074
    Abstract: A method of manufacturing a semiconductor substrate includes: heat-treating a germanium layer 30 with an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere at 700° C. or greater. Alternatively, a method of manufacturing a semiconductor substrate includes heat-treating a germanium layer 30 having an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere so that the oxygen concentration decreases.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: May 9, 2017
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira Toriumi, Choong-hyun Lee, Tomonori Nishimura
  • Publication number: 20160276445
    Abstract: A method of manufacturing a semiconductor substrate includes: heat-treating a germanium layer 30 with an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere at 700° C. or greater. Alternatively, a method of manufacturing a semiconductor substrate includes heat-treating a germanium layer 30 having an oxygen concentration of 1×1016 cm?3 or greater in a reducing gas atmosphere so that the oxygen concentration decreases.
    Type: Application
    Filed: October 10, 2014
    Publication date: September 22, 2016
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira TORIUMI, Choong-hyun LEE, Tomonori NISHIMURA
  • Publication number: 20160218182
    Abstract: A semiconductor structure includes: a germanium layer; and a first insulating film that is formed on an upper surface of the germanium layer, primarily contains germanium oxide and a substance having an oxygen potential lower than an oxygen potential of germanium oxide, and has a physical film thickness of 3 nm or less; wherein a half width of frequency to height in a 1 ?m square area of the upper surface of the germanium layer is 0.7 nm or less.
    Type: Application
    Filed: June 6, 2014
    Publication date: July 28, 2016
    Applicant: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Akira TORIUMI, Toshiyuki TABATA, Choong Hyun LEE, Tomonori NISHIMURA, Cimang LU
  • Publication number: 20100176478
    Abstract: Provided are a novel method and a novel structure for bringing a Ge or SiGe compound and a metal into ohmic contact with each other. A semiconductor device is provided with a portion composed of only i) Ge or SiGe compound, ii) a metal, and iii) an insulator or a semiconductor arranged between the material i) and the metal ii). In the semiconductor device, A) the material i) and the metal ii) have Schottky junction in the case where the holes of the material i) are majority carriers, and/or B) the material i) and the metal ii) are in an ohmic contact when the electrons of the material i) are majority carriers.
    Type: Application
    Filed: September 1, 2008
    Publication date: July 15, 2010
    Applicant: THE UNIVERSITY OF TOKYO
    Inventors: Akira Toriumi, Tomonori Nishimura
  • Patent number: 6858161
    Abstract: A method for purifying an electronic item material, which comprises dissolving an electronic item material or its intermediate product in an organic solvent and having the solution contacted with activated clay at a temperature of 65° C. to 200° C.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: February 22, 2005
    Assignee: Hodogaya Chemical Co., Ltd.
    Inventors: Katsumi Abe, Tomonori Nishimura, Takanobu Watanabe, Susumu Suzuka
  • Publication number: 20030050489
    Abstract: A method for purifying an electronic item material, which comprises dissolving an electronic item material or its intermediate product in an organic solvent and having the solution contacted with activated clay at a temperature of 65° C. to 200° C.
    Type: Application
    Filed: June 29, 2001
    Publication date: March 13, 2003
    Applicant: Hodogaya Chemical Co., Ltd.
    Inventors: Katsumi Abe, Tomonori Nishimura, Takanobu Watanabe, Susumu Suzuka