Patents by Inventor Tomoo Matsuzawa

Tomoo Matsuzawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7449786
    Abstract: A semiconductor device with improved the adhesion between bonding pads and ball portions of gold wires is provided to improve the reliability of a semiconductor device. About 1 wt. % of Pd is contained in gold wires for connection between electrode pads formed on a wiring substrate and electrode pads (exposed areas of a top layer wiring formed mainly of Al) formed on a semiconductor chip. In bonded portions between the electrode and ball portions of the gold wires, an interdiffusion of Au and Al is suppressed to prevent the formation of Au4Al after PCT (Pressure Cooker Test). Thus, a desired bonding strength is obtained even when the pitch of the electrode pads is smaller than 65 ?m and the diameter of the ball portion is smaller than 55 ?m or the diameter of the wire portion of each gold wire is not larger than 25 ?m.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: November 11, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Kawanabe, Tomoo Matsuzawa, Toshiaki Morita, Takafumi Nishita
  • Publication number: 20070187823
    Abstract: An object of the present invention is to establish, for an LSI having a stacked interconnection structure of Cu interconnect/Low-k material, a narrow pitch wire bonding technique enabling a reduction in damage to a bonding pad and application similar to the conventional LSI of an aluminum interconnection. In a semiconductor device having a multilayer interconnection made of a Cu interconnect/Low-k dielectric material, the above-described object can be attained by a bonding pad structure in which all the wiring layers up to the uppermost cap interconnect are formed of a Cu wiring layer and a bonding pad portion formed of a Cu layer is equipped with a refractory intermediate metal layer such as Ti (titanium) filmor (tungsten) film on the Cu layer and an aluminum alloy layer on the intermediate metal layer.
    Type: Application
    Filed: April 13, 2007
    Publication date: August 16, 2007
    Inventors: Naotaka Tanaka, Tomio Iwasaki, Hideo Miura, Yasuyuki Nakajima, Tomoo Matsuzawa
  • Patent number: 7199469
    Abstract: The cost of a semiconductor device is to be reduced. An electrical connection between a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip is made through an inner lead portion of a lead disposed at a position around the first semiconductor chip and two bonding wires.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: April 3, 2007
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd., Hitachi Hokkai Semiconductor, Ltd.
    Inventors: Toru Ishida, Tetsuharu Urawa, Fujio Ito, Tomoo Matsuzawa, Kazunari Suzuki, Akihiko Kameoka, Hiromichi Suzuki, Takuji Ide
  • Publication number: 20060138679
    Abstract: A semiconductor device with improved the adhesion between bonding pads and ball portions of gold wires is provided to improve the reliability of a semiconductor device. About 1 wt. % of Pd is contained in gold wires for connection between electrode pads formed on a wiring substrate and electrode pads (exposed areas of a top layer wiring formed mainly of Al) formed on a semiconductor chip. In bonded portions between the electrode and ball portions of the gold wires, an interdiffusion of Au and Al is suppressed to prevent the formation of Au4Al after PCT (Pressure Cooker Test). Thus, a desired bonding strength is obtained even when the pitch of the electrode pads is smaller than 65 ?m and the diameter of the ball portion is smaller than 55 ?m or the diameter of the wire portion of each gold wire is not larger than 25 ?m.
    Type: Application
    Filed: February 21, 2006
    Publication date: June 29, 2006
    Inventors: Naoki Kawanabe, Tomoo Matsuzawa, Toshiaki Morita, Takafumi Nishita
  • Patent number: 7049214
    Abstract: A method is provided to improve the adhesion between bonding pads and ball portions of gold wires to improve the reliability of a semiconductor device. About 1 wt. % of Pd is contained in gold wires for connection between electrode pads formed on a wiring substrate and electrode pads (exposed areas of a top layer wiring formed mainly of Al) formed on a semiconductor chip. In bonded portions between the electrode and ball portions of the gold wires, an interdiffusion of Au and Al is suppressed to prevent the formation of Au4Al after PCT (Pressure Cooker Test). Thus, a desired bonding strength is obtained even when the pitch of the electrode pads is smaller than 65 ?m and the diameter of the ball portion is smaller than 55 ?m or the diameter of the wire portion of each gold wire is not larger than 25 ?m.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: May 23, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Naoki Kawanabe, Tomoo Matsuzawa, Toshiaki Morita, Takafumi Nishita
  • Publication number: 20060091487
    Abstract: A sensor chip and a lens mount accommodating therein the sensor chip are mounted on a surface of a wiring substrate and a lens holder accommodating a lens therein is coupled with the lens mount. On a rear surface of the wiring substrate, a logic chip, a memory chip and a passive component are mounted and they are sealed with a seal resin. An electrode pad of the sensor chip is electrically connected to an electrode on the surface of the wiring substrate via a bonding wire but a stud bump is also formed on the electrode at the surface of the wiring substrate and this stud bump is connected with the bonding wire. On the surface of the wiring substrate, a flexible substrate is bonded with an anisotropic conductive film and a bonding material. When a camera module is to be manufactured, the surface side of the wiring substrate is assembled after the rear surface side of the wiring substrate is assembled.
    Type: Application
    Filed: December 16, 2005
    Publication date: May 4, 2006
    Inventors: Kenji Hanada, Masaki Nakanishi, Tomoo Matsuzawa, Koji Shida, Kazutoshi Takashima
  • Patent number: 7015127
    Abstract: Provided is a semiconductor device comprising a first metal film formed above a semiconductor chip, a ball portion formed over said first metal film and made of a second metal, and an alloy layer of said first metal and said second metal which alloy layer is formed between said first metal film and said ball portion, wherein said alloy layer reaches the bottom of said first metal film, and said ball portion is covered with a resin; and a manufacturing method thereof. The present invention makes it possible to improve adhesion between the bonding pad portion and ball portion of a bonding wire over an interconnect, thereby improving the reliability of the semiconductor device.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: March 21, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Yasuyuki Nakajima, Toshiaki Morita, Tomoo Matsuzawa, Seiichi Tomoi, Naoki Kawanabe
  • Patent number: 7005310
    Abstract: A sensor chip and a lens mount accommodating therein the sensor chip are mounted on a surface of a wiring substrate and a lens holder accommodating a lens therein is coupled with the lens mount. On a rear surface of the wiring substrate, a logic chip, a memory chip and a passive component are mounted and they are sealed with a seal resin. An electrode pad of the sensor chip is electrically connected to an electrode on the surface of the wiring substrate via a bonding wire but a stud bump is also formed on the electrode at the surface of the wiring substrate and this stud bump is connected with the bonding wire. On the surface of the wiring substrate, a flexible substrate is bonded with an anisotropic conductive film and a bonding material. When a camera module is to be manufactured, the surface side of the wiring substrate is assembled after the rear surface side of the wiring substrate is assembled.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: February 28, 2006
    Assignees: Renesas Technology Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Kenji Hanada, Masaki Nakanishi, Tomoo Matsuzawa, Koji Shida, Kazutoshi Takashima
  • Publication number: 20050121805
    Abstract: A semiconductor device comprising a plurality of wires for electrically connecting a plurality of electrode pads arranged on a main surface of a semiconductor chip along one side of the semiconductor chip to a plurality of connecting portions arranged on the main surface of a wiring substrate along one side of the semiconductor chip, respectively, wherein second wires out of the plural wires consisting of first and second wires adjacent to each other have a larger loop height than the first wires, one end portions of the second wires are connected to the electrode pads at positions farther from one side of the semiconductor chip than the one end portions of the first wires, and the other end portions of the second wires are connected to the connecting portions at positions farther from one side of the semiconductor chip than the other end portions of the first wires.
    Type: Application
    Filed: January 18, 2005
    Publication date: June 9, 2005
    Inventors: Tomoo Matsuzawa, Takafumi Nishita, Yasuyuki Nakajima, Toshiaki Morita
  • Patent number: 6900551
    Abstract: A semiconductor device comprising a plurality of wires for electrically connecting a plurality of electrode pads arranged on a main surface of a semiconductor chip along one side of the semiconductor chip to a plurality of connecting portions arranged on the main surface of a wiring substrate along one side of the semiconductor chip, respectively, wherein second wires out of the plural wires consisting of first and second wires adjacent to each other have a larger loop height than the first wires, one end portions of the second wires are connected to the electrode pads at positions farther from one side of the semiconductor chip than the one end portions of the first wires, and the other end portions of the second wires are connected to the connecting portions at positions farther from one side of the semiconductor chip than the other end portions of the first wires.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: May 31, 2005
    Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.
    Inventors: Tomoo Matsuzawa, Takafumi Nishita, Yasuyuki Nakajima, Toshiaki Morita
  • Patent number: 6897570
    Abstract: A highly reliable semiconductor device provided herein can prevent a junction between a pad and a wire from coming off, and pads from peeling off an underlying insulating layer on the interface thereof. The semiconductor device has plugs formed in a region in which an electrode pad is formed over a substrate. The plugs protrude into the electrode pad.
    Type: Grant
    Filed: January 9, 2003
    Date of Patent: May 24, 2005
    Assignee: Renesas Technology, Corporation
    Inventors: Takashi Nakajima, Naotaka Tanaka, Yasuyuki Nakajima, Ryo Haruta, Tomoo Matsuzawa, Masashi Sahara, Ken Okutani
  • Publication number: 20050035449
    Abstract: A method is provided to improve adhesion between bonding pads and ball portions of gold wires to improve reliability of a semiconductor device. About 1 wt. % of Pd is contained in gold wires for connection between electrode pads formed on a wiring substrate and electrode pads (exposed areas of a top layer wiring formed mainly of Al) formed on a semiconductor chip. In bonded portions between the electrode and ball portions of the gold wires, an interdiffusion of Au and Al is suppressed to prevent the formation of Au4A1 after POT (Pressure Cooker Test). Thus, a desired bonding strength is obtained even when the pitch of the electrode pads is smaller than 65 pin and the diameter of the ball portion is smaller than 55 pm or the diameter of the wire portion of each gold wire is not larger than 25 pin.
    Type: Application
    Filed: March 24, 2004
    Publication date: February 17, 2005
    Inventors: Naoki Kawanabe, Tomoo Matsuzawa, Toshiaki Morita, Takafumi Nishita
  • Publication number: 20050001314
    Abstract: An object of the present invention is to establish, for an LSI having a stacked interconnection structure of Cu interconnect/Low-k material, a narrow pitch wire bonding technique enabling a reduction in damage to a bonding pad and application similar to the conventional LSI of an aluminum interconnection. In a semiconductor device having a multilayer interconnection made of a Cu interconnect/Low-k dielectric material, the above-described object can be attained by a bonding pad structure in which all the wiring layers up to the uppermost cap interconnect are formed of a Cu wiring layer and a bonding pad portion formed of a Cu layer is equipped with a refractory intermediate metal layer such as Ti (titanium) filmor (tungsten) film on the Cu layer and an aluminum alloy layer on the intermediate metal layer.
    Type: Application
    Filed: June 23, 2004
    Publication date: January 6, 2005
    Inventors: Naotaka Tanaka, Tomio Iwasaki, Hideo Miura, Yasuyuki Nakajima, Tomoo Matsuzawa
  • Publication number: 20040166763
    Abstract: A sensor chip and a lens mount accommodating therein the sensor chip are mounted on a surface of a wiring substrate and a lens holder accommodating a lens therein is coupled with the lens mount. On a rear surface of the wiring substrate, a logic chip, a memory chip and a passive component are mounted and they are sealed with a seal resin. An electrode pad of the sensor chip is electrically connected to an electrode on the surface of the wiring substrate via a bonding wire but a stud bump is also formed on the electrode at the surface of the wiring substrate and this stud bump is connected with the bonding wire. On the surface of the wiring substrate, a flexible substrate is bonded with an anisotropic conductive film and a bonding material. When a camera module is to be manufactured, the surface side of the wiring substrate is assembled after the rear surface side of the wiring substrate is assembled.
    Type: Application
    Filed: August 29, 2003
    Publication date: August 26, 2004
    Inventors: Kenji Hanada, Masaki Nakanishi, Tomoo Matsuzawa, Koji Shida, Kazutoshi Takashima
  • Publication number: 20040142551
    Abstract: Provided is a semiconductor device comprising a first metal film formed above a semiconductor chip, a ball portion formed over said first metal film and made of a second metal, and an alloy layer of said first metal and said second metal which alloy layer is formed between said first metal film and said ball portion, wherein said alloy layer reaches the bottom of said first metal film, and said ball portion is covered with a resin; and a manufacturing method thereof. The present invention makes it possible to improve adhesion between the bonding pad portion and ball portion of a bonding wire over an interconnect, thereby improving the reliability of the semiconductor device.
    Type: Application
    Filed: April 8, 2003
    Publication date: July 22, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Yasuyuki Nakajima, Toshiaki Morita, Tomoo Matsuzawa, Seiichi Tomoi, Naoki Watanabe
  • Publication number: 20030230809
    Abstract: A highly reliable semiconductor device provided herein can prevent a junction between a pad and a wire from coming off, and pads from peeling off an underlying insulating layer on the interface thereof. The semiconductor device has plugs formed in a region in which an electrode pad is formed over a substrate. The plugs protrude into the electrode pad.
    Type: Application
    Filed: January 9, 2003
    Publication date: December 18, 2003
    Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takashi Nakajima, Naotaka Tanaka, Yasuyuki Nakajima, Ryo Haruta, Tomoo Matsuzawa, Masashi Sahara, Ken Okutani
  • Publication number: 20030218245
    Abstract: A semiconductor device comprising a plurality of wires for electrically connecting a plurality of electrode pads arranged on a main surface of a semiconductor chip along one side of the semiconductor chip to a plurality of connecting portions arranged on the main surface of a wiring substrate along one side of the semiconductor chip, respectively, wherein second wires out of the plural wires consisting of first and second wires adjacent to each other have a larger loop height than the first wires, one end portions of the second wires are connected to the electrode pads at positions farther from one side of the semiconductor chip than the one end portions of the first wires, and the other end portions of the second wires are connected to the connecting portions at positions farther from one side of the semiconductor chip than the other end portions of the first wires.
    Type: Application
    Filed: May 7, 2003
    Publication date: November 27, 2003
    Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Tomoo Matsuzawa, Takafumi Nishita, Yasuyuki Nakajima, Toshiaki Morita
  • Publication number: 20030168740
    Abstract: Provided is a semiconductor device comprising a first metal film formed above a semiconductor chip, a ball portion formed over said first metal film and made of a second metal, and an alloy layer of said first metal and said second metal which alloy layer is formed between said first metal film and said ball portion, wherein said alloy layer reaches the bottom of said first metal film, and said ball portion is covered with a resin; and a manufacturing method thereof. The present invention makes it possible to improve adhesion between the bonding pad portion and ball portion of a bonding wire over an interconnect, thereby improving the reliability of the semiconductor device.
    Type: Application
    Filed: February 21, 2003
    Publication date: September 11, 2003
    Inventors: Yasuyuki Nakajima, Toshiaki Morita, Tomoo Matsuzawa, Seiichi Tomoi, Naoki Kawanabe
  • Publication number: 20020043717
    Abstract: The cost of a semiconductor device is to be reduced. An electrical connection between a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip is made through an inner lead portion of a lead disposed at a position around the first semiconductor chip and two bonding wires.
    Type: Application
    Filed: September 28, 2001
    Publication date: April 18, 2002
    Inventors: Toru Ishida, Tetsuharu Urawa, Fujio Ito, Tomoo Matsuzawa, Kazunari Suzuki, Akihiko Kameoka, Hiromichi Suzuki, Takuji Ide
  • Patent number: 5252854
    Abstract: Disclosed is a resin-molded type semiconductor device having a thin package while avoiding short-circuit of wires with a common inner lead. In the construction thereof, a common inner lead constituted by a thin metal sheet is fixed onto a circuit-forming surface of a rectangular semiconductor chip substantially in parallel with longer sides of the chip and substantially in a central region of the chip, and a plurality of inner leads for signals, which are in the form of a frame, are stacked and fixed onto the common inner lead; then these components are molded with resin.
    Type: Grant
    Filed: June 18, 1991
    Date of Patent: October 12, 1993
    Assignees: Hitachi, Ltd., Hitachi Microcomputer
    Inventors: Junichi Arita, Akihiko Iwaya, Tomoo Matsuzawa, Masahiro Ichitani