Abstract: A supporting body includes a cluster of an alloy containing Pt and Co, and a support on which the cluster is supported. An amount of Pt supported is 1×10?14 ng/cm2 or more and 1×105 ng/cm2 or less.

Abstract: Provided is a method for producing metal nanoparticles, which enables metal nanoparticles to be more conveniently produced. The method for producing metal nanoparticles includes spraying and drying a mixture to form metal nanoparticles, the mixture containing a metal salt and at least one solvent selected from alcohols having 1 or more and 5 or less carbon atoms.

Abstract: An instruction code conversion unit, an information processing system provided with the instruction code conversion unit and an instruction code generation method for generating instruction codes which are converted by the instruction code conversion unit are described. The efficiency of coding of the program is improved by making use of an existing processor as selected is used without modification. An instruction code conversion unit performs conversion of the address of a native instruction code to the address of the corresponding compressed instruction code in a program memory by shifting the address of the native instruction code as outputted from the processor to the right by one bit.

Abstract: An instruction code conversion unit, an information processing system provided with the instruction code conversion unit and an instruction code generation method for generating instruction codes which are converted by the instruction code conversion unit are described. The efficiency of coding of the program is improved by making use of an existing processor as selected is used without modification. An instruction code conversion unit performs conversion of the address of a native instruction code to the address of the corresponding compressed instruction code in a program memory by shifting the address of the native instruction code as outputted from the processor to the right by one bit.

Abstract: In a semiconductor integrated circuit for switching various functions in accordance with "H"/"L" level of a read output from EPROM cells or the like, a state of memory cells incorporated in the semiconductor is detected to switch a function state. The semiconductor integrated circuit is free from an inoperative state caused by indefinite values of an initial state (erasure state) as of the EPROM cells and the like, or is free from a state in which only a predetermined operation is performed. When a writing operation is performed to EPROM cells and the like in an initial state in advance, a function test for a semiconductor integrated circuit can be normally performed. A test time can be largely decreased compared with that of a conventional technique, and a production cost can be largely reduced.

Abstract: A semiconductor substrate has a plurality of MOS transistors formed therein. Each of the transistors comprises high density diffusion regions having high impurity density and serving as source and drain, low density diffusion regions having low impurity density and extending in contact with the high density diffusion regions, respectively, a channel region formed between the low density diffusion regions, and a gate formed above the substrate and insulated from the channel region. One of the transistors has its drain connected to an input/output terminal. The low density diffusion region of the one has impurity density higher than that of the other. The channel length of the one is greater than that of the other.

Abstract: A charge pump circuit including a step-up section (1) having an output point to which a load is connected, the step-up section (1 ) having a function to step up an output potential from a predetermined potential lower than a potential (V.sub.PP) of a power supply to a desired potential higher than the power supply potential (V.sub.PP), wherein the charge pump circuit comprises initial potential setting switch (N.sub.10) connected between the power supply and the output point of the step-up section (1), and operative so that it is turned on with the beginning of the step-up operation of the step-up section (1) to propagate the power supply potential (V.sub.PP) to the output point of the step-up section (1), and that it is turned off in a suitable time. With the beginning of the step-up operation of the step-up section (1), the initial potential setting switch (N.sub.10) is turned on. As a result, a power supply potential (V.sub.PP) is propagated to the output point of the step-up section (1).

Abstract: An integrating circuit integrates an input signal. When an output from the integrating circuit is input to an AC coupling circuit, only an AC component of the output is extracted. The AC component which passes through the AC coupling circuit is waveshaped and coverted into a rectangular wave by a waveshaping circuit. The duty ratio of the waveshaped rectangular wave is detected by a duty ratio detecting circuit. A voltage corresponding to the duty ratio is then generated and fed back to the output of the AC coupling circuit through a feedback circuit. As a result, a DC bias component is applied to the AC component which has passed through the AC coupling circuit. In this case, the voltage generated by the duty ratio detecting circuit is controlled to coincide with the circuit threshold value of the waveshaping circuit, and a rectangular wave having a duty ratio of 50% is output from the waveshaping circuit.

Abstract: The present invention provides a logic circuit comprising a first power terminal, a second power terminal set at a higher potential than the first power terminal, a first FET of a first conductivity having a current path coupled to the first power terminal, a second FET of a second conductivity having a current path coupled to the second power terminal, and an input terminal commonly coupled to gate terminals of the first and second FETs, the first FET and the second FET having a relationship expressed approximately by the following equation: ##EQU1## where R.sub.S is a resistance of a resistor element parasitically produced between the first power terminal and the current path of the first FET. R.sub.D is a resistance of a resistor element parasitically produced between the second power terminal and the current path of the second FET, W.sub.N is a channel width of the first FET, W.sub.P is a channel width of the second FET, L.sub.N is a channel length of the first FET, L.sub.

Abstract: An inverter circuit according to this invention includes n- and p-type field effect transistors having predetermined wiring resistances and gates and drains connected with each other, a first power source connected to the source of the n-type field effect transistor, a power source connected to the source of the p-type field effect transistor, and first and second negative feedback switching transistors connected in parallel between the gates and the drains of the n- and p-type field effect transistors. Assuming that the channel length and width of the first insulating gate field effect transistor are L.sub.N and W.sub.N, respectively, and the wiring resistance thereof is R.sub.S, that the channel length and width of the second insulating gate field effect transistor are L.sub.P and W.sub.P, respectively, and the wiring resistance thereof is R.sub.D, and that carrier mobilities of the first and second insulating gate field effect transistors are .mu..sub.N and .mu..sub.

Abstract: One of analog input voltages applied to a plurality of analog input terminals is selected by means of analog switches connected to the respective analog input terminals and supplied to a common terminal. In this case, each of the analog switches permits selective supply of the potential of a corresponding one of the plurality of analog input terminals in response to a control signal supplied from a controller. The common terminal is connected to the positive input terminal of a comparator. The comparator compares the voltage with a digital output value from the controller which is converted into an analog voltage by means of a D/A converter. Further, the controller generates a preset control signal in an inhibition period during which supply of a voltage from the plurality of analog input terminals to the common terminal is inhibited.

Abstract: At least first and second IC-chip equivalent regions having functions available from conventional one-chip IC device are formed on a single semiconductor substrate. An output of the second region is supplied to an input terminal of the first region. The output of the second region is also delivered at an external terminal in response to a test signal through a multiplexer or a bidirectional buffer.

Abstract: A noise cancelling circuit includes a delay circuit for delaying an input signal which is supplied to an input terminal, and a signal processing circuit responsive to the input signal and an output signal from the delay circuit, to generate an output signal corresponding to the input signal. The signal processing circuit has a first switching circuit, which includes first and second switching elements connected in series between a first power supply terminal and an output, and a second switching circuit, which includes third and fourth switching elements connected in series between a second power supply terminal and the output, wherein the first and third switching elements are responsive to the aforementioned input signal, by which they are set in mutually opposite conduction states, and the second and fourth switching elements are responsive to the output signal of the delay circuit, by which they too are set in mutually opposite conduction states.

Abstract: A memory device with a register interchange function includes a register file with a plurality of registers, one of which is selected according to select signals, and a register select circuit. The internal memory state of the register select circuit is updated according to the internal memory state and a pair of interchange data for interchanging the select signals. In a register selection mode, a level setting of the select data is performed depending on the internal memory state and the register select data.

Abstract: A sweep circuit of a key matrix, has an output circuit wherein a series circuit of a pair of transistors with a terminal interposed therebetween is inserted between a power supply and a reference potential, and a timing pulse for selectively turning on one of said pair of transistors is supplied to the gates of the pair of transistors so as to produce a key scanning signal; an input circuit wherein a transistor is inserted between a terminal connecting an output side of the key matrix and the reference potential, the key matrix being connected between the terminals of the output and input circuits; and a transistor which switches to insert a current limiting resistor between the reference potential and the transistor at the reference potential side in each of the input and output circuits in the non-read-in mode.

Abstract: An electronic calculator includes a display section having segment LCDs, a key-in section having a plurality of key switches arranged in a matrix, and a one chip integrated calculation control unit connected to the display section and the key-in section for performing a calculation and a display in accordance with a key input signal. In the calculation control unit of the calculator, a common terminal is used for both a key output signal for detecting the key input signal and a segment signal for driving the display section. The common terminal is so set as to have a high impedance when the key switch is still closed after the end of one time processing of the key input signal.