Abstract: A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.

Abstract: A power storage device includes a welded portion in which a hole circumferential portion of a current collecting member and a swaged and deformed portion of a terminal member are welded, and a first space, which is surrounded by the welded portion, a hole circumferential surface of the hole circumferential portion, and the swaged and deformed portion, is placed adjacent to the welded portion to extend in a circumferential direction along the hole circumferential surface.

Abstract: A semiconductor device capable of changing a data programming process in a simple manner according to a situation is provided. The semiconductor device includes a plurality of memory cells, a programming circuit for supplying a programming current to the memory cell, and a power supply circuit for supplying power to the programming circuit. The power supply circuit includes a charge pump circuit for boosting the external power supply, a voltage of the external power supply according to the selection indication, and a selectable circuit capable of switching the boosted voltage boosted by the charge pump circuit. The control circuit further includes a control circuit for executing data programming processing by the programming circuit by switching the selection indication.

Abstract: A semiconductor device includes a logic circuit, a memory, and a storage device. The storage device has a first special information storage region into which special information is written before a solder reflow process, a second special information storage region into which special information for updating is written after the solder reflow process, and a data storage region. The first special information storage region is constituted by a memory cell having a high reflow resistance and in which data is retained even after the solder reflow process. The second special information storage region and the data storage region are constituted by memory cells having a low reflow resistance and in which data may not be retained during the solder reflow process.

Abstract: In a semiconductor device including a plurality of memory regions formed of split-gate type MONOS memories, threshold voltages of memory cells are set to different values for each memory region. Memory cells having different threshold voltages are formed by forming a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a data region, and a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a code region, of different materials or different thicknesses.

Abstract: A multiple-output load driving device includes a plurality of output terminals (OUT1 to OUT4) for outputting an output current to each of a plurality of loads (Z1 to Z4), a control portion (8) configured to select either a non-DC current mode in which a non-DC current is used as the output current or a DC current mode in which a DC current is used as the output current, and a first terminal (MSET2). In a case where a low-level signal is supplied to the first terminal, in the non-DC current mode, the non-DC current is outputted from all of the plurality of output terminals. In a case where a high-level signal is supplied to the first terminal, in the non-DC current mode, the DC current is outputted from a predetermined one (OUT4) of the output terminals, while the non-DC current is outputted from the other output terminals (OUT1 to OUT3).

Abstract: A multiple-output load driving device includes a plurality of output terminals (OUT1 to OUT4) for outputting an output current to each of a plurality of loads (Z1 to Z4), a control portion (8) configured to select either a non-DC current mode in which a non-DC current is used as the output current or a DC current mode in which a DC current is used as the output current, and a first terminal (MSET2). In a case where a low-level signal is supplied to the first terminal, in the non-DC current mode, the non-DC current is outputted from all of the plurality of output terminals. In a case where a high-level signal is supplied to the first terminal, in the non-DC current mode, the DC current is outputted from a predetermined one (OUT4) of the output terminals, while the non-DC current is outputted from the other output terminals (OUT1 to OUT3).

Abstract: It is to optimize the initial threshold voltages of each memory area in a semiconductor memory device including a plurality of memory areas. A semiconductor memory device according to the embodiment includes a first memory area for storing data and a second memory area for storing the information related to the first memory area. In the respective memory cells arranged in the first and the second memory areas, the initial threshold voltages of the memory cells arranged in the second memory area are designed to be higher than those of the memory cells arranged in the first memory area.

Abstract: A single-seat electric-vehicle travel control apparatus controls traveling of a single-seat electric vehicle by using output of a user-input detection device which has an input scheme different from those of conventionally proposed input apparatuses and which is highly versatile. A first user-input information acquisition unit acquires first user-input information, which indicates a first user action detected by the first user-input detection device. A second user-input information acquisition unit acquires second user-input information, which indicates a second user action detected by the second user-input detection device without contact with the second part of the user's body. A multi-input controller determines a first user intention based on first user-input information acquired by a first user-input information acquisition unit. The multi-input controller determines a second user intention based on second user-input information indicative of a second user action.

Abstract: An optical apparatus includes a first optical element and a second optical element capable of separating incident light according to a wavelength of the incident light. The first optical element includes a first separation section having first optical characteristics for reflecting light in a first wavelength band, transmitting light in a second wavelength band, and partially transmitting and partially reflecting light in a third wavelength band. The second optical element includes a second separation section having second optical characteristics for separating incident light that is incident in two wavelength bands including the first wavelength band or the second wavelength band and the third wavelength band into the light in the first wavelength band or the light in the second wavelength band and the light in the third wavelength band according to the wavelength.

Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.

Abstract: In a semiconductor device including a plurality of memory regions formed of split-gate type MONOS memories, threshold voltages of memory cells are set to different values for each memory region. Memory cells having different threshold voltages are formed by forming a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a data region, and a metal film, which is a work function film constituting a memory gate electrode of a memory cell in a code region, of different materials or different thicknesses.

Abstract: It is to optimize the initial threshold voltages of each memory area in a semiconductor memory device including a plurality of memory areas. A semiconductor memory device according to the embodiment includes a first memory area for storing data and a second memory area for storing the information related to the first memory area. In the respective memory cells arranged in the first and the second memory areas, the initial threshold voltages of the memory cells arranged in the second memory area are designed to be higher than those of the memory cells arranged in the first memory area.

Abstract: A memory cell of a split gate type MONOS memory is formed over a plate-shaped fin being a part of a semiconductor substrate. In a data erase operation, in a selected memory cell on which erasing is performed, a drain region is applied with 0 V, a memory gate electrode is applied with a positive voltage, and accordingly, erasing is performed by the FN mechanism. Also, in the data erase operation, in an unselected memory cell on which the erasing is not performed, connected to the same memory gate line as the above-described selected memory cell, the drain region is in an open state, and the memory gate electrode is applied with the positive voltage, whereby an induced voltage region is generated in a channel region. Thus, a potential difference between the channel region and the memory gate electrode is small, and accordingly, the erasing is not performed.

Abstract: Provided is a light-emitting element drive device including a transistor control unit arranged to drive and control a transistor connected to a light-emitting element, an output ground fault detection unit arranged to output an output ground fault detection signal corresponding to the voltage level at a connection node between the light-emitting element and the transistor, a stop control unit arranged to stop driving the transistor when the output ground fault detection signal indicates an output ground fault, and a mask signal generation unit arranged to generate a mask signal that masks the output ground fault detection signal on device startup.

Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.

Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.

Abstract: A semiconductor device according to one embodiment includes a unique ID generation circuit configured to generate a unique ID using a memory array including a plurality of complementary cells, each of the complementary cells includes first and second memory cells MC1 and MC2. The unique ID generation circuit uses, when data in the complementary cell read out in a first state in which an initial threshold voltage of the first memory cell MC1 has been virtually offset and data in the complementary cell read out in a second state in which an initial threshold voltage of the second memory cell MC2 has been virtually offset coincide with each other, the data in the complementary cell as the unique ID.

Abstract: A flash memory refreshes at a time before a read error might occur. A controller performs a first read operation and a second read operation using a sense amplifier. In the second read operation, a bit line potential controller draws out a potential of a bit line feeding the sense amplifier so that, if memory cell degradation has occurred, the degradation can be detected. For example, when first data read by the first read operation and second data read by the second read operation are determined to be different, the memory cell is refreshed.

Abstract: To downsize a semiconductor device that includes a non-volatile memory and a capacitive element on a semiconductor substrate. In a capacitive element region of a main surface of a semiconductor substrate, fins protruding from the main surface are arranged along the Y direction while extending in the X direction. In the capacitive element region of the main surface of the semiconductor substrate, capacitor electrodes of the capacitive elements are alternately arranged along the X direction while intersecting the fins. The fins are formed in a formation step of other fins which are arranged in a memory cell array of the non-volatile memory of the semiconductor substrate. One capacitor electrode is formed in a formation step of a control gate electrode of the non-volatile memory. Another capacitor electrode is formed in a formation step of a memory gate electrode of the non-volatile memory.