Patents by Inventor Tomoyoshi Kobori

Tomoyoshi Kobori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10789095
    Abstract: A data processing system includes a plurality of calculation processors cascaded and a plurality of counters connected to the plurality of calculation processors, respectively. The plurality of calculation processors process a task in an order in which the plurality of calculation processors are cascaded. A count value of an individual one of the plurality of counters is incremented when a corresponding one of the calculation processors starts to process a task and is decremented when a calculation processor in a lowermost stage among the plurality of calculation processors ends the task.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: September 29, 2020
    Assignee: NEC CORPORATION
    Inventor: Tomoyoshi Kobori
  • Patent number: 10437650
    Abstract: Provided is a processing apparatus, including: a plurality of processing unit; at least one or more data buffers that are connected between a first processing unit and a second processing unit and is able to store data output from the first processing unit and data input to the second processing unit; a command buffer that stores a task command specifying execution of a task to be executed in one or more specific processing units, the command buffer being able to output the task command to the processing unit; and a task control unit that is configured to control operational processing in the task, by controlling at least one of the data buffer and the command buffer, on the basis of the task command, task setting information representing the processing unit in which the task is executed, and information representing a state of operational processing in respective processing unit.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: October 8, 2019
    Assignee: NEC Corporation
    Inventor: Tomoyoshi Kobori
  • Publication number: 20180276037
    Abstract: A data processing system includes a plurality of calculation processors cascaded and a plurality of counters connected to the plurality of calculation processors, respectively. The plurality of calculation processors process a task in an order in which the plurality of calculation processors are cascaded. A count value of an individual one of the plurality of counters is incremented when a corresponding one of the calculation processors starts to process a task and is decremented when a calculation processor in a lowermost stage among the plurality of calculation processors ends the task.
    Type: Application
    Filed: March 16, 2018
    Publication date: September 27, 2018
    Applicant: NEC Corporation
    Inventor: Tomoyoshi KOBORI
  • Publication number: 20170147411
    Abstract: Provided is a processing apparatus, including: a plurality of processing unit; at least one or more data buffers that are connected between a first processing unit and a second processing unit and is able to store data output from the first processing unit and data input to the second processing unit; a command buffer that stores a task command specifying execution of a task to be executed in one or more specific processing units, the command buffer being able to output the task command to the processing unit; and a task control unit that is configured to control operational processing in the task, by controlling at least one of the data buffer and the command buffer, on the basis of the task command, task setting information representing the processing unit in which the task is executed, and information representing a state of operational processing in respective processing unit.
    Type: Application
    Filed: June 11, 2015
    Publication date: May 25, 2017
    Applicant: NEC Corporation
    Inventor: Tomoyoshi KOBORI
  • Patent number: 9507541
    Abstract: A computation device according to the present invention includes: a first data storage unit that stores operation target data; an operation processing unit that executes an operation by using data; a data permutation unit that selects indicated data among the operation target data stored in the first data storage unit and data operated by the operation processing unit, provides predetermined delay for data received a delay indication among the indicated data based on a parameter, does not delay data not received a delay indication, executes permutation of indicated data based on a parameter, and outputs data operated in the operation processing unit and operation result data of the operation processing unit; and second data storage unit that stores the operation result data output by the data permutation unit.
    Type: Grant
    Filed: December 16, 2013
    Date of Patent: November 29, 2016
    Assignee: NEC CORPORATION
    Inventor: Tomoyoshi Kobori
  • Patent number: 9424230
    Abstract: In an array processing section, using data strings entered from input ports, a plurality of data processor elements execute predetermined operations while transferring data to each other, and output data strings of results of the operations from a plurality of output ports. A first data string converter converts data strings stored in a plurality of data storages of a data storage group into a placement suitable for the operations in the array processing section, and enters the converted data strings into the input ports of the array processing section. A second data string converter converts the data strings output from output ports of the array processing section into a placement to be stored in the plurality of data storages of the data storage group.
    Type: Grant
    Filed: February 22, 2008
    Date of Patent: August 23, 2016
    Assignee: NEC CORPORATION
    Inventors: Tomoyoshi Kobori, Katsutoshi Seki
  • Patent number: 9367496
    Abstract: To provide a DMA transfer apparatus and a DMA transfer method capable of reducing traffic on a bus between an external shared memory and DMA controller with less additional hardware to effectively use a memory. A pattern generation section 11 is provided in a DMA controller 17 and generates data of a predetermined pattern, such as a zero matrix or unit matrix, in the DMA controller when data is transferred from an external shared memory 14 to an internal memory 15. Further, transfer data read out from the external shared memory is temporarily held in a queuing section 13 for queuing. At this time, switching between the transfer data from the queuing section and predetermined pattern data is made based on the number of the transfer data.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: June 14, 2016
    Assignee: NEC CORPORATION
    Inventor: Tomoyoshi Kobori
  • Patent number: 9250996
    Abstract: In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.
    Type: Grant
    Filed: October 4, 2011
    Date of Patent: February 2, 2016
    Assignees: NEC CORPORATION, TECHNISCHE UNIVERSITAT DRESDEN
    Inventors: Tomoyoshi Kobori, Steffen Kunze, Emil Matus, Gerhard Fettweis
  • Publication number: 20150347056
    Abstract: A computation device according to the present invention includes: a first data storage unit that stores operation target data; an operation processing unit that executes an operation by using data; a data permutation unit that selects indicated data among the operation target data stored in the first data storage unit and data operated by the operation processing unit, provides predetermined delay for data received a delay indication among the indicated data based on a parameter, does not delay data not received a delay indication, executes permutation of indicated data based on a parameter, and outputs data operated in the operation processing unit and operation result data of the operation processing unit; and second data storage unit that stores the operation result data output by the data permutation unit.
    Type: Application
    Filed: December 16, 2013
    Publication date: December 3, 2015
    Applicant: NEC CORPORATION
    Inventor: Tomoyoshi KOBORI
  • Publication number: 20150046563
    Abstract: An arithmetic processing device includes a first storage for storing processing contents in a state where the processing contents are associated with addresses, a second storage for storing each of the addresses of the processing contents stored in the first storage, a holding portion, a reading portion-for successively reading the addresses stored in the second storage and outputting the read addresses to the holding portion, and an execution portion for reading the processing content corresponding to the address output from the holding portion from the first storage and executing the read processing content. When the holding portion holds no address, the holding portion temporarily holds the address read by the reading portion and outputs the held address, whereas when the holding portion holds the address, the holding portion waits for completion of the execution of the processing content by the execution portion and outputs the held address after the completion of the execution.
    Type: Application
    Filed: February 13, 2013
    Publication date: February 12, 2015
    Applicant: NEC CORPORATION
    Inventor: Tomoyoshi Kobori
  • Patent number: 8694975
    Abstract: A first compiler generates one or more object codes from a program code for a first processor included in an arithmetic processing system to which a plurality of processors are mutually connected. A first linker links the generated one or more object codes to generate an execution file for the first processor. A parameter information generation unit generates, based on the information acquired from the first linker, parameter information used in a second processor included in the arithmetic processing system. A second compiler refers to a program code and the parameter information for the second processor to generate one or more object codes. A second linker links the generated one or more object codes to generate an execution file for the second processor.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: April 8, 2014
    Assignee: NEC Corporation
    Inventor: Tomoyoshi Kobori
  • Publication number: 20140040700
    Abstract: In a multicore type error correction processing system which can simultaneously cope with a plurality of error correction methods and a plurality of code lengths, an interconnect part 11 has a barrel shifter which extends across a plurality of error correction processing parts 12a-12c. An error correction process can be selectively performed by collectively using a group of the plurality of the error correction processing parts 12a-12c or by individually using each of individual error correction processing parts 12a-12c in response to interconnection configuration information. With this structure, the plurality of the error correction processing parts 12a-12c are collectively used if computation resources are insufficient and an idling error correction processing part is assigned to another error correction process if computation resources are excessive.
    Type: Application
    Filed: October 4, 2011
    Publication date: February 6, 2014
    Inventors: Tomoyoshi Kobori, Steffen Kunze, Emil Matus, Gerhard Fettweis
  • Patent number: 8452943
    Abstract: In address generation processors, the start and the end of the processing for address generation need to be controlled in addition to controlling the processing for base address generation. A timing control unit manages control for address conversion on a clock cycle basis. The difference between the processing speed in the address generation processors and the processing speed in the address conversion circuit is absorbed by buffers.
    Type: Grant
    Filed: December 5, 2008
    Date of Patent: May 28, 2013
    Assignee: NEC Corporation
    Inventor: Tomoyoshi Kobori
  • Patent number: 8446951
    Abstract: To provide a dynamic image receiving apparatus which receives dynamic image streams coded with inter-frame prediction such as MPEG from a plurality of channels, and collects the dynamic image streams containing intra-frame coded pictures from each channel in a short time. The dynamic image receiving apparatus includes: a time information accumulative processing device which accumulates code receiving time of the intra-frame coded picture of the dynamic image stream, and periodicity time information containing one of or both of presentation time information and decoding time information contained in the dynamic image stream for each dynamic image stream of the plurality of channels; code receiving time predicting devices which predict the code receiving time of the intra-frame coded pictures based on the periodicity time information; and a channel selection control device which controls channel selection of the dynamic image stream to be received based on the predicted code receiving time information.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: May 21, 2013
    Assignee: NEC Corporation
    Inventors: Katsunori Tanaka, Atsushi Hatabu, Yuzo Senda, Katsutoshi Seki, Tomoyoshi Kobori, Kosuke Nishihara, Soji Mori
  • Publication number: 20110167417
    Abstract: A first compiler generates one or more object codes from a program code for a first processor included in an arithmetic processing system to which a plurality of processors are mutually connected. A first linker links the generated one or more object codes to generate an execution file for the first processor. A parameter information generation unit generates, based on the information acquired from the first linker, parameter information used in a second processor included in the arithmetic processing system. A second compiler refers to a program code and the parameter information for the second processor to generate one or more object codes. A second linker links the generated one or more object codes to generate an execution file for the second processor.
    Type: Application
    Filed: July 23, 2009
    Publication date: July 7, 2011
    Inventor: Tomoyoshi Kobori
  • Publication number: 20100306496
    Abstract: In address generation processors, the start and the end of the processing for address generation need to be controlled in addition to controlling the processing for base address generation. A timing control unit manages control for address conversion on a clock cycle basis. The difference between the processing speed in the address generation processors and the processing speed in the address conversion circuit is absorbed by buffers.
    Type: Application
    Filed: December 5, 2008
    Publication date: December 2, 2010
    Inventor: Tomoyoshi Kobori
  • Publication number: 20100246673
    Abstract: To provide a dynamic image receiving apparatus which receives dynamic image streams coded with inter-frame prediction such as MPEG from a plurality of channels, and collects the dynamic image streams containing intra-frame coded pictures from each channel in a short time. The dynamic image receiving apparatus includes: a time information accumulative processing device which accumulates code receiving time of the intra-frame coded picture of the dynamic image stream, and periodicity time information containing one of or both of presentation time information and decoding time information contained in the dynamic image stream for each dynamic image stream of the plurality of channels; code receiving time predicting devices which predict the code receiving time of the intra-frame coded pictures based on the periodicity time information; and a channel selection control device which controls channel selection of the dynamic image stream to be received based on the predicted code receiving time information.
    Type: Application
    Filed: September 19, 2008
    Publication date: September 30, 2010
    Applicant: NEC CORPORATION
    Inventors: Katsunori Tanaka, Atsushi Hatabu, Yuzo Senda, Katsutoshi SEKI, Tomoyoshi Kobori, Kosuke Nishihara, Soji Mori
  • Publication number: 20100131738
    Abstract: In an array processing section, using data strings entered from input ports, a plurality of data processor elements execute predetermined operations while transferring data to each other, and output data strings of results of the operations from a plurality of output ports. A first data string converter converts data strings stored in a plurality of data storages of a data storage group into a placement suitable for the operations in the array processing section, and enters the converted data strings into the input ports of the array processing section. A second data string converter converts the data strings output from output ports of the array processing section into a placement to be stored in the plurality of data storages of the data storage group.
    Type: Application
    Filed: February 22, 2008
    Publication date: May 27, 2010
    Inventors: Tomoyoshi Kobori, Katsutoshi Seki
  • Publication number: 20100106865
    Abstract: To provide a DMA transfer apparatus and a DMA transfer method capable of reducing traffic on a bus between an external shared memory and DMA controller with less additional hardware to effectively use a memory. A pattern generation section 11 is provided in a DMA controller 17 and generates data of a predetermined pattern, such as a zero matrix or unit matrix, in the DMA controller when data is transferred from an external shared memory 14 to an internal memory 15. Further, transfer data read out from the external shared memory is temporarily held in a queuing section 13 for queuing. At this time, switching between the transfer data from the queuing section and predetermined pattern data is made based on the number of the transfer data.
    Type: Application
    Filed: February 28, 2008
    Publication date: April 29, 2010
    Inventor: Tomoyoshi Kobori