Patents by Inventor Tomoyoshi Mishima
Tomoyoshi Mishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11640906Abstract: Provided is a crystal laminate including: a crystal substrate formed from a monocrystal of group III nitride expressed by a compositional formula InxAlyGa1-x-yN (where 0?x?1, 0?y?1, 0?x+y?1), the crystal substrate containing at least any one of n-type impurity selected from the group consisting of Si, Ge, and O; and a crystal layer formed by a group III nitride crystal epitaxially grown on a main surface of the crystal substrate, at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb being ion-implanted in the crystal layer. The crystal laminate is configured in a manner such that an absorption coefficient of the crystal substrate for light with a wavelength of 2000 nm when the crystal substrate is irradiated with the light falls within a range of 1.8 cm?1 or more and 4.6 cm?1 or less under a temperature condition of normal temperature.Type: GrantFiled: April 19, 2018Date of Patent: May 2, 2023Assignees: SUMITOMO CHEMICAL COMPANY, LIMITED, HOSEI UNIVERSITYInventors: Fumimasa Horikiri, Takehiro Yoshida, Tomoyoshi Mishima
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Patent number: 10998188Abstract: There is provided a gallium nitride laminated substrate including: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.Type: GrantFiled: May 6, 2019Date of Patent: May 4, 2021Assignees: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Tomoyoshi Mishima, Hiroshi Ohta, Fumimasa Horikiri, Masatomo Shibata
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Patent number: 10797181Abstract: A semiconductor device is included a first semiconductor layer with n-type conductivity, containing a gallium nitride-based semiconductor, a second semiconductor layer with p-type conductivity, which is laminated directly on the first semiconductor layer and contains a gallium nitride-based semiconductor added with a p-type impurity at a concentration of 1×1020 cm?3 or more, a first electrode disposed in contact with the first semiconductor layer, and a second electrode disposed in contact with the second semiconductor layer, and the semiconductor device functions as a pn-junction diode.Type: GrantFiled: June 27, 2017Date of Patent: October 6, 2020Assignees: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Tomoyoshi Mishima, Fumimasa Horikiri
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Publication number: 20200227262Abstract: Provided is a crystal laminate including: a crystal substrate formed from a monocrystal of group III nitride expressed by a compositional formula InxAlyGa1-x-yN (where 0?x?1, 0?y?1, 0?x+y?1), the crystal substrate containing at least any one of n-type impurity selected from the group consisting of Si, Ge, and O; and a crystal layer formed by a group III nitride crystal epitaxially grown on a main surface of the crystal substrate, at least any one of p-type impurity selected from the group consisting of C, Mg, Fe, Be, Zn, V, and Sb being ion-implanted in the crystal layer. The crystal laminate is configured in a manner such that an absorption coefficient of the crystal substrate for light with a wavelength of 2000 nm when the crystal substrate is irradiated with the light falls within a range of 1.8 cm?1 or more and 4.6 cm?1 or less under a temperature condition of normal temperature.Type: ApplicationFiled: April 19, 2018Publication date: July 16, 2020Applicants: SUMITOMO CHEMICAL COMPANY, LIMITED, SCIOCS COMPANY LIMITED, HOSEI UNIVERSITYInventors: Fumimasa HORIKIRI, Takehiro YOSHIDA, Tomoyoshi MISHIMA
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Patent number: 10685841Abstract: A semiconductor device includes a semiconductor member having a mesa structure in which a first semiconductor layer and a second semiconductor layer are laminated on each other and having a pn junction; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode connected to the first semiconductor layer on a lower surface of the first semiconductor layer, and having a capacitance of the insulating film when a reverse bias voltage is applied between the first electrode and the second electrode, so that a first voltage applied to the insulating film between a corner position (a first position) where the side surface of the insulating film disposed on the side surface of the mesa structure anType: GrantFiled: August 23, 2016Date of Patent: June 16, 2020Assignees: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Tohru Nakamura, Tomoyoshi Mishima, Hiroshi Ohta, Yasuhiro Yamamoto, Fumimasa Horikiri
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Publication number: 20200091016Abstract: A manufacturing method of a group-III nitride laminate includes: preparing a group-III nitride laminate having a group-III nitride substrate and a group-III nitride epitaxial layer formed above a main surface of the group-III nitride substrate; and conducting photoluminescence mapping measurement at a plurality of measurement positions on the group-III nitride epitaxial layer, where a magnitude of an off-angle is different, the off-angle being formed by a normal direction of the main surface of the group-III nitride substrate and c-axis direction, to obtain a relative yellow intensity which is a rate of a yellow emission intensity to a band edge emission intensity, and obtain a correspondence relationship between a magnitude of the off-angle and the relative yellow intensity.Type: ApplicationFiled: November 9, 2017Publication date: March 19, 2020Inventors: Fumimasa HORIKIRI, Tomoyoshi MISHIMA
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Patent number: 10483350Abstract: There is provided a semiconductor device, including: a semiconductor member having a mesa structure in which a second semiconductor layer having one of a p-type conductivity type and an n-type conductivity type is laminated on a first semiconductor layer having the other one of the p-type conductivity type and the n-type conductivity type, so that the second semiconductor layer is exposed on an upper surface of the mesa structure, a pn junction interface is exposed on a side surface of the mesa structure, and the first semiconductor layer is exposed on an outside upper surface of the mesa structure; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode electrically connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode electrically connecType: GrantFiled: August 23, 2016Date of Patent: November 19, 2019Assignees: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Tohru Nakamura, Tomoyoshi Mishima, Hiroshi Ohta, Yasuhiro Yamamoto, Fumimasa Horikiri
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Publication number: 20190348276Abstract: There is provided a gallium nitride laminated substrate including: an n-type gallium nitride layer containing an n-type impurity; a p-type gallium nitride layer provided on the n-type gallium nitride layer, containing a p-type impurity, forming a pn-junction at an interface with the n-type gallium nitride layer, and having a p-type impurity concentration and a thickness such that, when a reverse bias voltage is applied to the pn-junction, a breakdown occurs due to a punchthrough phenomenon before occurrence of a breakdown due to an avalanche phenomenon; and an intermediate level layer provided on the p-type gallium nitride layer, containing a p-type gallium nitride which contains the p-type impurity at a higher concentration than the p-type gallium nitride layer, having at least one or more intermediate levels between a valence band and a conduction band, and configured to suppress an overcurrent resulting from a breakdown due to the punchthrough phenomenon in the p-type gallium nitride layer.Type: ApplicationFiled: May 6, 2019Publication date: November 14, 2019Inventors: Tomoyoshi MISHIMA, Hiroshi OHTA, Fumimasa HORIKIRI, Masatomo SHIBATA
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Publication number: 20190189808Abstract: A semiconductor device is included a first semiconductor layer with n-type conductivity, containing a gallium nitride-based semiconductor, a second semiconductor layer with p-type conductivity, which is laminated directly on the first semiconductor layer and contains a gallium nitride-based semiconductor added with a p-type impurity at a concentration of 1×1020 cm?3 or more, a first electrode disposed in contact with the first semiconductor layer, and a second electrode disposed in contact with the second semiconductor layer, and the semiconductor device functions as a pn-junction diode.Type: ApplicationFiled: June 27, 2017Publication date: June 20, 2019Inventors: Tomoyoshi MISHIMA, Fumimasa HORIKIRI
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Publication number: 20190181010Abstract: A semiconductor device includes a semiconductor member having a mesa structure in which a first semiconductor layer and a second semiconductor layer are laminated on each other and having a pn junction; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode connected to the first semiconductor layer on a lower surface of the first semiconductor layer, and having a capacitance of the insulating film when a reverse bias voltage is applied between the first electrode and the second electrode, so that a first voltage applied to the insulating film between a corner position (a first position) where the side surface of the insulating film disposed on the side surface of the mesa structure anType: ApplicationFiled: August 23, 2016Publication date: June 13, 2019Applicants: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Tohru NAKAMURA, Tomoyoshi MISHIMA, Hiroshi OHTA, Yasuhiro YAMAMOTO, Fumimasa HORIKIRI
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Publication number: 20180261667Abstract: There is provided a semiconductor device, including: a semiconductor member having a mesa structure in which a second semiconductor layer having one of a p-type conductivity type and an n-type conductivity type is laminated on a first semiconductor layer having the other one of the p-type conductivity type and the n-type conductivity type, so that the second semiconductor layer is exposed on an upper surface of the mesa structure, a pn junction interface is exposed on a side surface of the mesa structure, and the first semiconductor layer is exposed on an outside upper surface of the mesa structure; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode electrically connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode electrically connecType: ApplicationFiled: August 23, 2016Publication date: September 13, 2018Applicants: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Tohru NAKAMURA, Tomoyoshi MISHIMA, Hiroshi OHTA, Yasuhiro YAMAMOTO, Fumimasa HORIKIRI
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Patent number: 9899570Abstract: There is provided a semiconductor multilayer structure, including: an n-type GaN layer; and a p-type GaN layer which is formed on the n-type GaN layer and into which Mg is ion-implanted, and generating an electroluminescence emission having a peak at a photon energy of 3.0 eV or more, by applying a voltage to a pn-junction formed by the n-type GaN layer and the p-type GaN layer.Type: GrantFiled: June 5, 2015Date of Patent: February 20, 2018Assignee: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Naoki Kaneda, Tomoyoshi Mishima, Tohru Nakamura
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Publication number: 20170141270Abstract: There is provided a semiconductor multilayer structure, including: an n-type GaN layer; and a p-type GaN layer which is formed on the n-type GaN layer and into which Mg is ion-implanted, and generating an electroluminescence emission having a peak at a photon energy of 3.0 eV or more, by applying a voltage to a pn-junction formed by the n-type GaN layer and the p-type GaN layer.Type: ApplicationFiled: June 5, 2015Publication date: May 18, 2017Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventors: Naoki KANEDA, Tomoyoshi MISHIMA, Tohru NAKAMURA
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Patent number: 9530858Abstract: Disclosed are an npn-type bipolar transistor as a nitride semiconductor device having good characteristics, and a method of manufacturing the same. A so-called pn epitaxial substrate has a structure wherein an n-type collector layer and a p-type base layer of a three-layer structure are provided over a substrate. The three-layer structure includes first (lower layer side), second, and third (upper layer side) p-type base layers which differ in thickness and p-type impurity concentration. In a partial region inside the second p-type base layer located as an intermediate layer in the p-type base layer of the three-layer structure, an n-type emitter region is formed by ion implantation.Type: GrantFiled: December 24, 2014Date of Patent: December 27, 2016Assignee: Sumitomo Chemical Company, LimitedInventors: Akihisa Terano, Tomonobu Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima
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Publication number: 20150179780Abstract: Disclosed are an npn-type bipolar transistor as a nitride semiconductor device having good characteristics, and a method of manufacturing the same. A so-called pn epitaxial substrate has a structure wherein an n-type collector layer and a p-type base layer of a three-layer structure are provided over a substrate. The three-layer structure includes first (lower layer side), second, and third (upper layer side) p-type base layers which differ in thickness and p-type impurity concentration. In a partial region inside the second p-type base layer located as an intermediate layer in the p-type base layer of the three-layer structure, an n-type emitter region is formed by ion implantation.Type: ApplicationFiled: December 24, 2014Publication date: June 25, 2015Inventors: Akihisa TERANO, Tomonobu TSUCHIYA, Naoki KANEDA, Tomoyoshi MISHIMA
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Patent number: 9059328Abstract: A nitride semiconductor element having a high reverse breakdown voltage and a method of manufacturing the same are provided. A diode (a vertical-type SBD) has an n?-type nitride semiconductor layer (a drift region) formed on an n-type nitride semiconductor substrate, a p-type nitride semiconductor layer formed on the n?-type nitride semiconductor layer, and besides, an anode electrode formed on the p-type nitride semiconductor layer. The p-type nitride semiconductor layer has a relatively-thin first portion and a relatively-thick second portion provided so as to surround the first portion as being in contact with an outer circumference of the first portion. Also, the relatively-thin first portion of the p-type nitride semiconductor layer is formed thinner than the second portion so as to be depleted. The relatively-thick second portion of the p-type nitride semiconductor layer forms a guard ring part.Type: GrantFiled: October 29, 2013Date of Patent: June 16, 2015Assignee: Hitachi Metals, Ltd.Inventors: Akihisa Terano, Kazuhiro Mochizuki, Tomonobu Tsuchiya, Tadayoshi Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima
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Patent number: 8835930Abstract: A gallium nitride rectifying device includes a p-type gallium nitride based semiconductor layer and an n-type gallium nitride based semiconductor layer, the two layers forming a pn junction with each other. The p-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1018 cm?3, or the n-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1016 cm?3.Type: GrantFiled: March 21, 2012Date of Patent: September 16, 2014Assignee: Hitachi Metals, Ltd.Inventors: Tadayoshi Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima
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Publication number: 20140191369Abstract: A nitride semiconductor device includes a first nitride semiconductor layer, and an npn junction structure including a second nitride semiconductor layer of an n-type conductivity, a third nitride semiconductor layer of a p-type conductivity, and a fourth nitride semiconductor layer of an n-type conductivity layered in this order on the first nitride semiconductor layer. The third nitride semiconductor layer includes two or more uncovered regions which are uncovered with the fourth nitride semiconductor layer.Type: ApplicationFiled: October 31, 2013Publication date: July 10, 2014Applicant: Hitachi Metals, Ltd.Inventors: Tadayoshi TSUCHIYA, Naoki KANEDA, Tomoyoshi MISHIMA
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Publication number: 20140117376Abstract: A nitride semiconductor element having a high reverse breakdown voltage and a method of manufacturing the same are provided. A diode (a vertical-type SBD) has an n?-type nitride semiconductor layer (a drift region) formed on an n-type nitride semiconductor substrate, a p-type nitride semiconductor layer formed on the n?-type nitride semiconductor layer, and besides, an anode electrode formed on the p-type nitride semiconductor layer. The p-type nitride semiconductor layer has a relatively-thin first portion and a relatively-thick second portion provided so as to surround the first portion as being in contact with an outer circumference of the first portion. Also, the relatively-thin first portion of the p-type nitride semiconductor layer is formed thinner than the second portion so as to be depleted. The relatively-thick second portion of the p-type nitride semiconductor layer forms a guard ring part.Type: ApplicationFiled: October 29, 2013Publication date: May 1, 2014Applicant: Hitachi Metals, Ltd.Inventors: Akihisa TERANO, Kazuhiro MOCHIZUKI, Tomonobu TSUCHIYA, Tadayoshi TSUCHIYA, Naoki KANEDA, Tomoyoshi MISHIMA
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Publication number: 20130001585Abstract: A gallium nitride rectifying device includes a p-type gallium nitride based semiconductor layer and an n-type gallium nitride based semiconductor layer, the two layers forming a pn junction with each other. The p-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1018 cm?3, or the n-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1016 cm?3.Type: ApplicationFiled: March 21, 2012Publication date: January 3, 2013Applicant: Hitachi Cable, Ltd.Inventors: Tadayoshi TSUCHIYA, Naoki KANEDA, Tomoyoshi MISHIMA