Patents by Inventor Tomoyoshi Mishima

Tomoyoshi Mishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190189808
    Abstract: A semiconductor device is included a first semiconductor layer with n-type conductivity, containing a gallium nitride-based semiconductor, a second semiconductor layer with p-type conductivity, which is laminated directly on the first semiconductor layer and contains a gallium nitride-based semiconductor added with a p-type impurity at a concentration of 1×1020 cm?3 or more, a first electrode disposed in contact with the first semiconductor layer, and a second electrode disposed in contact with the second semiconductor layer, and the semiconductor device functions as a pn-junction diode.
    Type: Application
    Filed: June 27, 2017
    Publication date: June 20, 2019
    Inventors: Tomoyoshi MISHIMA, Fumimasa HORIKIRI
  • Publication number: 20190181010
    Abstract: A semiconductor device includes a semiconductor member having a mesa structure in which a first semiconductor layer and a second semiconductor layer are laminated on each other and having a pn junction; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode connected to the first semiconductor layer on a lower surface of the first semiconductor layer, and having a capacitance of the insulating film when a reverse bias voltage is applied between the first electrode and the second electrode, so that a first voltage applied to the insulating film between a corner position (a first position) where the side surface of the insulating film disposed on the side surface of the mesa structure an
    Type: Application
    Filed: August 23, 2016
    Publication date: June 13, 2019
    Applicants: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Tohru NAKAMURA, Tomoyoshi MISHIMA, Hiroshi OHTA, Yasuhiro YAMAMOTO, Fumimasa HORIKIRI
  • Publication number: 20180261667
    Abstract: There is provided a semiconductor device, including: a semiconductor member having a mesa structure in which a second semiconductor layer having one of a p-type conductivity type and an n-type conductivity type is laminated on a first semiconductor layer having the other one of the p-type conductivity type and the n-type conductivity type, so that the second semiconductor layer is exposed on an upper surface of the mesa structure, a pn junction interface is exposed on a side surface of the mesa structure, and the first semiconductor layer is exposed on an outside upper surface of the mesa structure; an insulating film disposed on a side surface of the mesa structure and on an outside upper surface of the mesa structure; a first electrode electrically connected to the second semiconductor layer on the upper surface of the mesa structure, and extends on the side surface of the mesa structure and on the outside upper surface of the mesa structure on the insulating film; and a second electrode electrically connec
    Type: Application
    Filed: August 23, 2016
    Publication date: September 13, 2018
    Applicants: HOSEI UNIVERSITY, SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Tohru NAKAMURA, Tomoyoshi MISHIMA, Hiroshi OHTA, Yasuhiro YAMAMOTO, Fumimasa HORIKIRI
  • Patent number: 9899570
    Abstract: There is provided a semiconductor multilayer structure, including: an n-type GaN layer; and a p-type GaN layer which is formed on the n-type GaN layer and into which Mg is ion-implanted, and generating an electroluminescence emission having a peak at a photon energy of 3.0 eV or more, by applying a voltage to a pn-junction formed by the n-type GaN layer and the p-type GaN layer.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: February 20, 2018
    Assignee: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Naoki Kaneda, Tomoyoshi Mishima, Tohru Nakamura
  • Publication number: 20170141270
    Abstract: There is provided a semiconductor multilayer structure, including: an n-type GaN layer; and a p-type GaN layer which is formed on the n-type GaN layer and into which Mg is ion-implanted, and generating an electroluminescence emission having a peak at a photon energy of 3.0 eV or more, by applying a voltage to a pn-junction formed by the n-type GaN layer and the p-type GaN layer.
    Type: Application
    Filed: June 5, 2015
    Publication date: May 18, 2017
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Naoki KANEDA, Tomoyoshi MISHIMA, Tohru NAKAMURA
  • Patent number: 9530858
    Abstract: Disclosed are an npn-type bipolar transistor as a nitride semiconductor device having good characteristics, and a method of manufacturing the same. A so-called pn epitaxial substrate has a structure wherein an n-type collector layer and a p-type base layer of a three-layer structure are provided over a substrate. The three-layer structure includes first (lower layer side), second, and third (upper layer side) p-type base layers which differ in thickness and p-type impurity concentration. In a partial region inside the second p-type base layer located as an intermediate layer in the p-type base layer of the three-layer structure, an n-type emitter region is formed by ion implantation.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: December 27, 2016
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Akihisa Terano, Tomonobu Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima
  • Publication number: 20150179780
    Abstract: Disclosed are an npn-type bipolar transistor as a nitride semiconductor device having good characteristics, and a method of manufacturing the same. A so-called pn epitaxial substrate has a structure wherein an n-type collector layer and a p-type base layer of a three-layer structure are provided over a substrate. The three-layer structure includes first (lower layer side), second, and third (upper layer side) p-type base layers which differ in thickness and p-type impurity concentration. In a partial region inside the second p-type base layer located as an intermediate layer in the p-type base layer of the three-layer structure, an n-type emitter region is formed by ion implantation.
    Type: Application
    Filed: December 24, 2014
    Publication date: June 25, 2015
    Inventors: Akihisa TERANO, Tomonobu TSUCHIYA, Naoki KANEDA, Tomoyoshi MISHIMA
  • Patent number: 9059328
    Abstract: A nitride semiconductor element having a high reverse breakdown voltage and a method of manufacturing the same are provided. A diode (a vertical-type SBD) has an n?-type nitride semiconductor layer (a drift region) formed on an n-type nitride semiconductor substrate, a p-type nitride semiconductor layer formed on the n?-type nitride semiconductor layer, and besides, an anode electrode formed on the p-type nitride semiconductor layer. The p-type nitride semiconductor layer has a relatively-thin first portion and a relatively-thick second portion provided so as to surround the first portion as being in contact with an outer circumference of the first portion. Also, the relatively-thin first portion of the p-type nitride semiconductor layer is formed thinner than the second portion so as to be depleted. The relatively-thick second portion of the p-type nitride semiconductor layer forms a guard ring part.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: June 16, 2015
    Assignee: Hitachi Metals, Ltd.
    Inventors: Akihisa Terano, Kazuhiro Mochizuki, Tomonobu Tsuchiya, Tadayoshi Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima
  • Patent number: 8835930
    Abstract: A gallium nitride rectifying device includes a p-type gallium nitride based semiconductor layer and an n-type gallium nitride based semiconductor layer, the two layers forming a pn junction with each other. The p-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1018 cm?3, or the n-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1016 cm?3.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: September 16, 2014
    Assignee: Hitachi Metals, Ltd.
    Inventors: Tadayoshi Tsuchiya, Naoki Kaneda, Tomoyoshi Mishima
  • Publication number: 20140191369
    Abstract: A nitride semiconductor device includes a first nitride semiconductor layer, and an npn junction structure including a second nitride semiconductor layer of an n-type conductivity, a third nitride semiconductor layer of a p-type conductivity, and a fourth nitride semiconductor layer of an n-type conductivity layered in this order on the first nitride semiconductor layer. The third nitride semiconductor layer includes two or more uncovered regions which are uncovered with the fourth nitride semiconductor layer.
    Type: Application
    Filed: October 31, 2013
    Publication date: July 10, 2014
    Applicant: Hitachi Metals, Ltd.
    Inventors: Tadayoshi TSUCHIYA, Naoki KANEDA, Tomoyoshi MISHIMA
  • Publication number: 20140117376
    Abstract: A nitride semiconductor element having a high reverse breakdown voltage and a method of manufacturing the same are provided. A diode (a vertical-type SBD) has an n?-type nitride semiconductor layer (a drift region) formed on an n-type nitride semiconductor substrate, a p-type nitride semiconductor layer formed on the n?-type nitride semiconductor layer, and besides, an anode electrode formed on the p-type nitride semiconductor layer. The p-type nitride semiconductor layer has a relatively-thin first portion and a relatively-thick second portion provided so as to surround the first portion as being in contact with an outer circumference of the first portion. Also, the relatively-thin first portion of the p-type nitride semiconductor layer is formed thinner than the second portion so as to be depleted. The relatively-thick second portion of the p-type nitride semiconductor layer forms a guard ring part.
    Type: Application
    Filed: October 29, 2013
    Publication date: May 1, 2014
    Applicant: Hitachi Metals, Ltd.
    Inventors: Akihisa TERANO, Kazuhiro MOCHIZUKI, Tomonobu TSUCHIYA, Tadayoshi TSUCHIYA, Naoki KANEDA, Tomoyoshi MISHIMA
  • Publication number: 20130001585
    Abstract: A gallium nitride rectifying device includes a p-type gallium nitride based semiconductor layer and an n-type gallium nitride based semiconductor layer, the two layers forming a pn junction with each other. The p-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1018 cm?3, or the n-type gallium nitride based semiconductor layer has a carrier trap (level) density of not more than 1×1016 cm?3.
    Type: Application
    Filed: March 21, 2012
    Publication date: January 3, 2013
    Applicant: Hitachi Cable, Ltd.
    Inventors: Tadayoshi TSUCHIYA, Naoki KANEDA, Tomoyoshi MISHIMA
  • Publication number: 20120313108
    Abstract: To provide a semiconductor diode with a part of a semiconductor lamination portion having a mesa structure portion, which is the part where a pn-junction is formed by lamination of an n-type semiconductor layer and a p-type semiconductor layer on a substrate, comprising: a protective insulating film formed by coating a main surface of the mesa structure portion, a side face of the mesa structure portion in which an interface of the pn-junction is exposed, and an etched and exposed surface of the n-type semiconductor layer; and an anode electrode formed in ohmic-contact with the p-type semiconductor layer exposed from an opening formed on a part of the main surface of the mesa structure portion of the protective insulating film, extending from the main surface, through the side face of the mesa structure portion, to the surface of the n-type semiconductor layer.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 13, 2012
    Applicant: HITACHI CABLE, LTD.
    Inventors: Tadayoshi TSUCHIYA, Naoki KANEDA, Tomoyoshi MISHIMA, Toshihiro KAWANO, Toru NAKAMURA, Kazuki NOMOTO
  • Patent number: 7786509
    Abstract: A field-effect transistor is composed of a substrate, an electron transport layer and an electron supply layer formed sequentially on the substrate, wherein the electron transport layer and the electron supply layer are formed of a nitride semiconductor, a gate electrode, a source electrode and a drain electrode formed on the electron supply layer; and two high impurity concentration regions located in a depth direction directly below the source electrode and the drain electrode, respectively, the two high impurity concentration regions being formed to sandwich a two-dimensional electron gas layer formed between the electron transport layer and the electron supply layer. The two high impurity concentration regions each have a higher impurity concentration than the electron transport layer and the electron supply layer located directly below the gate electrode.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: August 31, 2010
    Assignee: Hitachi Cable, Ltd.
    Inventors: Tomoyoshi Mishima, Toru Nakamura, Masataka Sato, Kazutaka Nomoto
  • Publication number: 20090026499
    Abstract: A semiconductor integrated circuit device having a plurality of semiconductor electronic members including a field effect transistor, intended for suppressing a sidegating effect on the field effect transistor, wherein accumulation of majority carriers of the field effect transistor is suppressed at the interface of heterojunction in the buffering compound semiconductor layer and the interface between the substrate and the buffering compound semiconductor layer in the device isolation region so that the discontinuity of energy forbidden bands of the semiconductors caused at the interfaces does not form a potential barrier upon conduction of the carriers into the substrate, whereby the sidegating effect from the resistor element, etc. placed adjacently to the field effect transistor can be decreased drastically.
    Type: Application
    Filed: January 24, 2008
    Publication date: January 29, 2009
    Inventors: Takeshi Kikawa, Shinichiro Takatani, Tomihisa Yukimoto, Yohei Otoki, Hiroyuki Kamogawa, Tomoyoshi Mishima
  • Publication number: 20090001423
    Abstract: A field-effect transistor is composed of a substrate, an electron transport layer and an electron supply layer formed sequentially on the substrate, wherein the electron transport layer and the electron supply layer are formed of a nitride semiconductor, a gate electrode, a source electrode and a drain electrode formed on the electron supply layer; and two high impurity concentration regions located in a depth direction directly below the source electrode and the drain electrode, respectively, the two high impurity concentration regions being formed to sandwich a two-dimensional electron gas layer formed between the electron transport layer and the electron supply layer. The two high impurity concentration regions each have a higher impurity concentration than the electron transport layer and the electron supply layer located directly below the gate electrode.
    Type: Application
    Filed: September 26, 2007
    Publication date: January 1, 2009
    Inventors: Tomoyoshi Mishima, Toru Nakamura, Masataka Sato, Kazutaka Nomoto
  • Patent number: 6735353
    Abstract: The present invention provides a module for optical transmitter formed as an opto-electronic integrated circuit (OEIC) for reducing the heat generated at a driver circuit for modulator and stabilizing the thermal fluctuation in an optical modulator. For promoting the heat dissipation of the top face of the driver circuit for modulator of the OEIC chip, a protruding cooling plate is formed on metal wiring. A part of a semiconductor substrate present between the optical modulator and the driver circuit for modulator is thinned or removed. Further, a carrier for mounting thereon the OEIC chip is divided into two parts, and a peltier cooler is connected to the optical modulator side. This achieves the promotion of heat dissipation from the top face of the driver circuit for modulator, the thermal separation between the optical modulator and the driver circuit for modulator, and the temperature stabilization due to the peltier cooler.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: May 11, 2004
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co. Ltd.
    Inventors: Koji Hirata, Masataka Shirai, Tomoyoshi Mishima
  • Patent number: 6728283
    Abstract: A semiconductor laser which has an active layer of a lattice strain of less than 2% of a thickness mean on a GaAs substrate and can be used in a long wavelength band of 1.3 &mgr;m band or more and a photo module which uses the semiconductor laser are provided. The semiconductor laser device has a first semiconductor layer 5 and second semiconductor layers 4, the layer 5 and the layers 4 forming a type-II heterojunction structure, in which an energy of conduction band edge of said first conductor layer 5 is larger than the energy of conduction band of said second semiconductor layers 4. The device has third semiconductor layers 6 as barrier layers formed on both sides of said type-II heterojunction structure.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: April 27, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Kudo, Kiyoshi Ouchi, Tomoyoshi Mishima
  • Publication number: 20030142928
    Abstract: The present invention provides a module for optical transmitter formed as an opto-electronic integrated circuit (OEIC) for reducing the heat generated at a driver circuit for modulator and stabilizing the thermal fluctuation in an optical modulator.
    Type: Application
    Filed: November 22, 2002
    Publication date: July 31, 2003
    Applicant: Hitachi, Ltd and Hitachi ULSI Systems Co., Ltd.
    Inventors: Koji Hirata, Masataka Shirai, Tomoyoshi Mishima
  • Publication number: 20030132496
    Abstract: On an In-containing compound semiconductor are sequentially formed Zn (p-type dopant-containing layer), Ta (high-melting metal layer) and a low-resistance conductor layer in this order as a Schottky electrode, and the resulting assemblage is annealed to diffuse Zn into the semiconductor to thereby convert the surface of the semiconductor layer only in a region in contact with the Schottky electrode metal into a p-type layer. The p-type dopant-containing layer can be, instead of Zn, a compound between Zn and an element constituting the In-containing compound semiconductor or a Zn—Ta alloy. The high-melting metal layer can be, instead of Ta, an intermetallic compound between Ta and an element constituting the In-containing compound semiconductor or a Zn—Ta alloy.
    Type: Application
    Filed: November 19, 2002
    Publication date: July 17, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Akihisa Terano, Hiroshi Ohta, Kiyoshi Ouchi, Tomoyoshi Mishima