Abstract: To provide a semiconductor diode with a part of a semiconductor lamination portion having a mesa structure portion, which is the part where a pn-junction is formed by lamination of an n-type semiconductor layer and a p-type semiconductor layer on a substrate, comprising: a protective insulating film formed by coating a main surface of the mesa structure portion, a side face of the mesa structure portion in which an interface of the pn-junction is exposed, and an etched and exposed surface of the n-type semiconductor layer; and an anode electrode formed in ohmic-contact with the p-type semiconductor layer exposed from an opening formed on a part of the main surface of the mesa structure portion of the protective insulating film, extending from the main surface, through the side face of the mesa structure portion, to the surface of the n-type semiconductor layer.

Abstract: A field-effect transistor is composed of a substrate, an electron transport layer and an electron supply layer formed sequentially on the substrate, wherein the electron transport layer and the electron supply layer are formed of a nitride semiconductor, a gate electrode, a source electrode and a drain electrode formed on the electron supply layer; and two high impurity concentration regions located in a depth direction directly below the source electrode and the drain electrode, respectively, the two high impurity concentration regions being formed to sandwich a two-dimensional electron gas layer formed between the electron transport layer and the electron supply layer. The two high impurity concentration regions each have a higher impurity concentration than the electron transport layer and the electron supply layer located directly below the gate electrode.

Abstract: A semiconductor integrated circuit device having a plurality of semiconductor electronic members including a field effect transistor, intended for suppressing a sidegating effect on the field effect transistor, wherein accumulation of majority carriers of the field effect transistor is suppressed at the interface of heterojunction in the buffering compound semiconductor layer and the interface between the substrate and the buffering compound semiconductor layer in the device isolation region so that the discontinuity of energy forbidden bands of the semiconductors caused at the interfaces does not form a potential barrier upon conduction of the carriers into the substrate, whereby the sidegating effect from the resistor element, etc. placed adjacently to the field effect transistor can be decreased drastically.

Abstract: A field-effect transistor is composed of a substrate, an electron transport layer and an electron supply layer formed sequentially on the substrate, wherein the electron transport layer and the electron supply layer are formed of a nitride semiconductor, a gate electrode, a source electrode and a drain electrode formed on the electron supply layer; and two high impurity concentration regions located in a depth direction directly below the source electrode and the drain electrode, respectively, the two high impurity concentration regions being formed to sandwich a two-dimensional electron gas layer formed between the electron transport layer and the electron supply layer. The two high impurity concentration regions each have a higher impurity concentration than the electron transport layer and the electron supply layer located directly below the gate electrode.

Abstract: The present invention provides a module for optical transmitter formed as an opto-electronic integrated circuit (OEIC) for reducing the heat generated at a driver circuit for modulator and stabilizing the thermal fluctuation in an optical modulator. For promoting the heat dissipation of the top face of the driver circuit for modulator of the OEIC chip, a protruding cooling plate is formed on metal wiring. A part of a semiconductor substrate present between the optical modulator and the driver circuit for modulator is thinned or removed. Further, a carrier for mounting thereon the OEIC chip is divided into two parts, and a peltier cooler is connected to the optical modulator side. This achieves the promotion of heat dissipation from the top face of the driver circuit for modulator, the thermal separation between the optical modulator and the driver circuit for modulator, and the temperature stabilization due to the peltier cooler.

Abstract: A semiconductor laser which has an active layer of a lattice strain of less than 2% of a thickness mean on a GaAs substrate and can be used in a long wavelength band of 1.3 &mgr;m band or more and a photo module which uses the semiconductor laser are provided. The semiconductor laser device has a first semiconductor layer 5 and second semiconductor layers 4, the layer 5 and the layers 4 forming a type-II heterojunction structure, in which an energy of conduction band edge of said first conductor layer 5 is larger than the energy of conduction band of said second semiconductor layers 4. The device has third semiconductor layers 6 as barrier layers formed on both sides of said type-II heterojunction structure.

Abstract: The present invention provides a module for optical transmitter formed as an opto-electronic integrated circuit (OEIC) for reducing the heat generated at a driver circuit for modulator and stabilizing the thermal fluctuation in an optical modulator.

Abstract: On an In-containing compound semiconductor are sequentially formed Zn (p-type dopant-containing layer), Ta (high-melting metal layer) and a low-resistance conductor layer in this order as a Schottky electrode, and the resulting assemblage is annealed to diffuse Zn into the semiconductor to thereby convert the surface of the semiconductor layer only in a region in contact with the Schottky electrode metal into a p-type layer. The p-type dopant-containing layer can be, instead of Zn, a compound between Zn and an element constituting the In-containing compound semiconductor or a Zn—Ta alloy. The high-melting metal layer can be, instead of Ta, an intermetallic compound between Ta and an element constituting the In-containing compound semiconductor or a Zn—Ta alloy.

Abstract: A semiconductor laser which has an active layer of a lattice strain of less than 2% of a thickness mean on a GaAs substrate and can be used in a long wavelength band of 1.3 &mgr;m band or more and a photo module which uses the semiconductor laser are provided.

Abstract: A semiconductor device with improved heat radiation characteristics that is formed by employing a lattice-mismatched system semiconductor thin-film crystal layered product. In fabricating an HBT on a semi-insulating GaAs substrate, the HBT comprised of a material system lattice-matched to InP that is different from the substrate in the lattice constant, a structure is employed that comprises alloy compound semiconductor layers with thermal resistivities that increase with increasing lattice constant (e.g., InxGa1−xAs) and alloy compound semiconductor layers with thermal resistivities that decrease with increasing lattice constant (e.g., InyGa1−yP) as a lattice-strain-relaxed buffer layer. By using the above-mentioned lattice-strain-relaxed buffer layer, the thermal resistivity of the buffer layer can be reduced compared to a lattice-strain-relaxed buffer layer consisting of only InxGa1−xAs materials and a lattice-strain-relaxed buffer layer consisting of only InyGa1−yP materials.

Abstract: In order to provide a high-output field effect transistor having adopted such a structure that a heterointerface between an arsenic compound and a phosphoric compound does not influence the property of a device, and a high-output obtainable high frequency module equipped with MMIC fabricated using the field effect transistor, the field effect transistor having at least a channel layer through which electrons travel, an electron supply layer for supplying electrons to the channel layer, and a buffer layer for flattening the channel layer is provided with an inserted layer larger in bandgap than the buffer layer, which is formed between the buffer layer and the channel layer. This structure can be realized by, for example, achieving the substrate side of the channel layer as an InP layer, the inserted layer as InAlP layer, and the buffer layer as an InAlAs layer respectively.

Abstract: A semiconductor device has a lattice-mismatched crystal structure including a semiconductor film formed on a substrate with an intervening buffer layer. The buffer layer has a plurality of layers, including first sublayers, or regions, in which an element that controls the lattice constant is provided in increasing mole fraction, and second sublayers, or regions, in which the lattice constant is maintained. The first sublayers and second sublayers are provided in alternating fashion. The resulting device has an increased electron mobility as compared with the prior art.

Abstract: In a semiconductor device using tunnel current and a barrier layer, arrangements are provided to lower the resistance of the semiconductor device. In particular, arrangements are provided to lower the parasitic resistance of a device such as a field effect transistor or an HBT, as well as to provide high-performance low noise amplifiers, mixers and the like using such reduced resistance semiconductor devices. To achieve this reduced resistance, carrier concentration or effective mass is designed not to be uniform in at least one of the semiconductor layers holding a barrier layer therebetween. For example, in an area near the barrier layer, the carrier concentration distribution can be large or the effective mass distribution can be small.

Abstract: A semiconductor crystalline laminate structure wherein between a first semiconductor layer consisting of a first alloyed semiconductor and a second semiconductor layer which has an energy gap wider than that of the first alloyed semiconductor and a lattice constant smaller than that of the first alloyed semiconductor and consists of one semiconductor selected from a group of single-element semiconductor, compound semiconductor, and alloyed semiconductor which contain no semiconductor having a largest lattice constant among the semiconductor constituting the first alloyed semiconductor, a third semiconductor layer which consists of a second alloyed semiconductor having an energy gap wider than that of the first alloyed semiconductor and contains the semiconductor having a largest lattice constant among the semiconductors constituting the first alloyed semiconductor is formed in contact with these layers, a forming method for the semiconductor crystalline laminate structure, and a semiconductor device using the

Abstract: Disclosed is a semiconductor device using a polycrystalline compound semiconductor with a low resistance as a low resistance layer, and its fabrication method. The above polycrystalline compound semiconductor layer is doped with C or Be as impurities in a large amount, and is extremely low in resistance. The polycrystalline compound semiconductor layer is formed by either of a molecular beam epitaxy method, an organometallic vapor phase epitaxy method and an organometallic molecular beam epitaxy method under the condition that a substrate temperature is 450.degree. C. or less and the ratio of partial pressure of a V-group element to a III-group element is 50 or more.

Abstract: The present invention provides a hetero-junction bipolar transistor (HBT) whichis so designed that the emitter injection efficiency is improved, the base transit time and base resistance are reduced and yet the lowering of the collector injection efficiency is suppressed, by forming at least one quantum well in a base region of the HBT and determining the width of one of the quantum levels formed in the quantum well and the energy in a barrier layer constituting the quantum well is within kT/2.

Abstract: A compound semiconductor structure in the form of a superlattice film with effectively graded average composition, comprising an alternating lamination of two kinds of layers of different composition to form pairs of layers, the ratio of the thickness of one layer to the thickness of the other in said pairs of layers being gradually varied in the direction of thickness throughout successive pairs, thereby the average composition being effectively graded throughout the pairs. In a hetero-junction field effect transistor, the layer of effectively graded composition is used between a semiconductor layer making low resistance contact with a current-supplying electrode and a semiconductor layer where a two dimensional channel is to be formed. In case of AlGaAs/GaAs system, the Al composition is varied. When the superlattice film is heat-treated, Al in the AlGaAs layer diffuses into the GaAs layer, yielding a film with actually smoothly graded Al mole fraction.

Abstract: An epitaxial crystal grown layer structure which permits, on an In-doped GaAs substrate, which will be industrially used in large quantities, the growth of an epitaxial layer having the same good quality as the epitaxial layer grown on an undoped GaAs substrate.

Abstract: There is disclosed a semiconductor device comprising at least first and second semiconductor layers positioned to form a hetero-junction therebetween, such a hetero-junction being adapted to form a channel, means for controlling carriers, and source and drain areas on opposite edges of the channel, wherein the first and second semiconductor layers formed between the source and drain regions have an area containing only 10.sup.16 cm.sup.-3 or less of an impurity; the first semiconductor layer has a wider forbidden band than that of the second semiconductor layer; and further including at least one semiconductor layer having a higher activation efficiency of impurities than that of the first semiconductor layer, with such at least one semiconductor layer being located on the side of the first semiconductor layer not in contact with the second semiconductor layer. A multi-quantum well structure may be used as the higher impurity activation efficiency semiconductor layer.

Abstract: A semiconductor member has a structure wherein a first semiconductor layer is held between second and third semiconductor layers which have forbidden band widths greater than a forbidden band width of the first semiconductor layer, and wherein only the second semiconductor layer which is formed on a side of the first semiconductor layer close to a substrate is doped with impurities. The semiconductor member constructs the depletion type with the first and second semiconductor layers, and the enhancement type with the first and third semiconductor layers. A semiconductor device can be properly formed in the enhancement or depletion type by selectively connecting the semiconductor layers.