Patents by Inventor Tomoyuki Akahoshi

Tomoyuki Akahoshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190306981
    Abstract: A circuit substrate includes a first insulating layer, a capacitor disposed over the first insulating layer, the capacitor including a dielectric layer, a first conductor layer disposed on a first face of the dielectric layer, and a second conductor layer disposed on a second face opposite to the first face of the dielectric layer and having an electric resistivity higher than that of the first conductor layer, a third conductor layer disposed on a surface of the second conductor layer, the third conductor layer having an electric resistivity lower than that of the second conductor layer, a second insulating layer covering the capacitor, and a conductor via disposed in the second insulating layer, the conductor via being coupled to a portion of the third conductor layer.
    Type: Application
    Filed: January 31, 2019
    Publication date: October 3, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Masaharu Furuyama, Daisuke Mizutani, Tomoyuki AKAHOSHI
  • Publication number: 20190306982
    Abstract: A circuit board includes an insulator layer, an electronic component built into the insulator layer, a first via penetrating the insulator layer, a second via extending from one surface of the insulator layer and coupled to the electronic component, and a metal layer formed over the one surface of the insulator layer, wherein a via pad is formed over the second via, an opening is formed between the metal layer and a first via side of the via pad, and the opposite side of the via pad to the first via side is coupled to the metal layer.
    Type: Application
    Filed: February 8, 2019
    Publication date: October 3, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Hideaki Nagaoka, Tomoyuki AKAHOSHI, Daisuke Mizutani
  • Publication number: 20190289718
    Abstract: A substrate includes: a signal line via, a ground line via, and a power supply line via; a first group of first conductor layers formed at a first wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a second conductor layer formed at a second wiring layer level and coupled to the power supply line via; a second group of third conductor layers formed at a third wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a first insulating layer; and a second insulating layer, wherein the second insulating layer has an opening with a third insulating layer, a relative dielectric constant of the second insulating layer is higher than the first insulating layer and the third insulating layer, and the opening reaches a conductor pattern.
    Type: Application
    Filed: June 7, 2019
    Publication date: September 19, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki Akahoshi, Daisuke Mizutani
  • Patent number: 10396020
    Abstract: A board includes a plate-shaped member having a first wiring pattern, a first resin layer formed on a first surface of the plate-shaped member, the first surface having the first wiring pattern, a second resin layer stacked on the first resin layer, and a component fixed to the second resin layer in which a second wiring pattern formed on a second surface of the component is buried.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: August 27, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Kei Fukui, Youichi Hoshikawa, Hiromitsu Kobayashi, Hidehiko Fujisaki, Seigo Yamawaki, Masateru Koide, Manabu Watanabe, Daisuke Mizutani, Tomoyuki Akahoshi
  • Patent number: 10362677
    Abstract: A substrate includes: a signal line via, a ground line via, and a power supply line via; a first group of first conductor layers formed at a first wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a second conductor layer formed at a second wiring layer level and coupled to the power supply line via; a second group of third conductor layers formed at a third wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a first insulating layer; and a second insulating layer, wherein the second insulating layer has an opening with a third insulating layer, a relative dielectric constant of the second insulating layer is higher than the first insulating layer and the third insulating layer, and the opening reaches a conductor pattern.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: July 23, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Tomoyuki Akahoshi, Daisuke Mizutani
  • Publication number: 20190215963
    Abstract: A circuit board includes a first capacitor that includes a first dielectric layer, a first conductor layer disposed on a first surface of the first dielectric layer, and a second conductor layer disposed on a second surface of the first dielectric layer opposite to the first surface, a first insulating layer that is bonded to the first surface side with a first adhesive layer and has a higher elastic modulus than the first adhesive layer, and a second insulating layer that is bonded to the second surface side with a second adhesive layer and has a higher elastic modulus than the second adhesive layer.
    Type: Application
    Filed: March 15, 2019
    Publication date: July 11, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki Akahoshi, Hideaki Nagaoka, Daisuke Mizutani
  • Publication number: 20190053385
    Abstract: A circuit board includes: an insulating layer; a capacitor which is provided in the insulating layer and which includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including an opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a recess part at a position corresponding to the opening part; and a conductor via provided in the insulating layer, penetrating the dielectric layer, the opening part and the recess part, being in contact with the recess part, and being smaller than the opening part in plan view.
    Type: Application
    Filed: October 17, 2018
    Publication date: February 14, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Masaharu Furuyama, Daisuke Mizutani, Tomoyuki AKAHOSHI, Masateru Koide, MANABU WATANABE, Seigo Yamawaki, Kei FUKUI
  • Publication number: 20190051598
    Abstract: A circuit board includes an insulating layer, a capacitor which is provided in the insulating layer and includes a dielectric layer, a first conductor layer provided on a first surface of the dielectric layer and including a first opening part, and a second conductor layer provided on a second surface opposite to the first surface of the dielectric layer and including a second opening part at a position corresponding to the first opening part; a first conductor via provided in the insulating layer, penetrating the dielectric layer, the first opening part and the second opening part, and being smaller than the first opening part and the second opening part in plan view; a second conductor via provided in the insulating layer and making contact with the second conductor layer; and a third conductor layer provided on the insulating layer and electrically coupled to the first and the second conductor vias.
    Type: Application
    Filed: October 18, 2018
    Publication date: February 14, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki AKAHOSHI, Masaharu Furuyama, Daisuke Mizutani
  • Publication number: 20180332707
    Abstract: A substrate includes: a signal line via, a ground line via, and a power supply line via; a first group of first conductor layers formed at a first wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a second conductor layer formed at a second wiring layer level and coupled to the power supply line via; a second group of third conductor layers formed at a third wiring layer level and coupled to the signal line via, the ground line via, and the power supply line via; a first insulating layer; and a second insulating layer, wherein the second insulating layer has an opening with a third insulating layer, a relative dielectric constant of the second insulating layer is higher than the first insulating layer and the third insulating layer, and the opening reaches a conductor pattern.
    Type: Application
    Filed: July 24, 2018
    Publication date: November 15, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki Akahoshi, Daisuke Mizutani
  • Publication number: 20180315687
    Abstract: A board includes a plate-shaped member having a first wiring pattern, a first resin layer formed on a first surface of the plate-shaped member, the first surface having the first wiring pattern, a second resin layer stacked on the first resin layer, and a component fixed to the second resin layer in which a second wiring pattern formed on a second surface of the component is buried.
    Type: Application
    Filed: April 19, 2018
    Publication date: November 1, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Kei FUKUI, Youichi Hoshikawa, Hiromitsu KOBAYASHI, Hidehiko Fujisaki, Seigo Yamawaki, Masateru Koide, MANABU WATANABE, Daisuke Mizutani, Tomoyuki AKAHOSHI
  • Patent number: 9491860
    Abstract: A wiring board includes a first insulating layer; a first wire that is provided at a first surface of the first insulating layer and transmits a first signal; and a second wire that is provided at a second surface of the first insulating layer that is opposite to the first surface, includes a first portion that is parallel to at least a portion of the first wire, and transmits a first component of the first signal that is transmitted through the first wire.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: November 8, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Tomoyuki Akahoshi
  • Patent number: 9179539
    Abstract: A wiring board includes a first wiring line and a second wiring line formed on a substrate, a first land and a second land respectively formed at a connection portion of the first wiring line and the second wiring line. A second wiring line has a longer wiring length than the first wiring line. The land is structured with a wiring pattern of a single wiring line. The wiring board also includes a first pad electrode and a second pad electrode respectively formed on the first land and a second land through an insulating film, a first interlayer connection via and a interlayer connection via embedded in the insulating film and electrically connecting the land to the pad electrode. And a wiring length of the wiring pattern of the first land is longer than the wiring length of the wiring pattern of the second land.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: November 3, 2015
    Assignee: FUJITSU LIMITED
    Inventor: Tomoyuki Akahoshi
  • Publication number: 20150214104
    Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of metal terminals that are formed on a surface of the semiconductor substrate on the opposite side to a circuit-forming surface; and a resin that is formed on the surface of the semiconductor substrate on the opposite side to the circuit-forming surface, and covers at least part of side surfaces of the metal terminals, wherein upper surfaces of the metal terminals are exposed from the resin.
    Type: Application
    Filed: April 7, 2015
    Publication date: July 30, 2015
    Inventor: Tomoyuki AKAHOSHI
  • Publication number: 20150189751
    Abstract: A wiring board includes a conductor formed on an inner wall of a through hole made in a core board, resin formed inside the conductor in the through hole, and, for example, a land formed over the conductor and the resin. Vias are formed over the land. The vias are connected to a plurality of connection regions of the land extending over the conductor and the resin in the through hole. The land is held by the vias connected to the plurality of connection regions. This controls the thermal expansion of the resin to a land side and therefore prevents a fracture of the land.
    Type: Application
    Filed: December 9, 2014
    Publication date: July 2, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Tomoyuki AKAHOSHI, Daisuke Mizutani, Motoaki Tani
  • Publication number: 20150000967
    Abstract: A wiring board includes a first insulating layer; a first wire that is provided at a first surface of the first insulating layer and transmits a first signal; and a second wire that is provided at a second surface of the first insulating layer that is opposite to the first surface, includes a first portion that is parallel to at least a portion of the first wire, and transmits a first component of the first signal that is transmitted through the first wire.
    Type: Application
    Filed: June 9, 2014
    Publication date: January 1, 2015
    Applicant: FUJITSU LIMITED
    Inventor: Tomoyuki AKAHOSHI
  • Publication number: 20140202752
    Abstract: A wiring board includes a first wiring line and a second wiring line formed on a substrate, a first land and a second land respectively formed at a connection portion of the first wiring line and the second wiring line. A second wiring line has a longer wiring length than the first wiring line. The land is structured with a wiring pattern of a single wiring line. The wiring board also includes a first pad electrode and a second pad electrode respectively formed on the first land and a second land through an insulating film, a first interlayer connection via and a interlayer connection via embedded in the insulating film and electrically connecting the land to the pad electrode. And a wiring length of the wiring pattern of the first land is longer than the wiring length of the wiring pattern of the second land.
    Type: Application
    Filed: November 11, 2013
    Publication date: July 24, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Tomoyuki AKAHOSHI
  • Publication number: 20130341765
    Abstract: A semiconductor device includes: a semiconductor substrate; a plurality of metal terminals that are formed on a surface of the semiconductor substrate on the opposite side to a circuit-forming surface; and a resin that is formed on the surface of the semiconductor substrate on the opposite side to the circuit-forming surface, and covers at least part of side surfaces of the metal terminals, wherein upper surfaces of the metal terminals are exposed from the resin.
    Type: Application
    Filed: April 24, 2013
    Publication date: December 26, 2013
    Applicant: Fujitsu Limited
    Inventor: Tomoyuki AKAHOSHI
  • Publication number: 20100244274
    Abstract: A wiring board includes a first conductor constituting a signal line, a second conductor constituting a ground conductor or a power conductor, a dielectric layer disposed between and separately the first and second conductors, and a third conductor arranged between the first and second conductor, the third conductor being connected to the second conductor, and having a width narrower than that of the first conductor, the third conductor entirely opposing the first conductor, the entire portion of the third conductor being covered by the first conductor.
    Type: Application
    Filed: March 19, 2010
    Publication date: September 30, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi ISHITSUKA, Tomoyuki Akahoshi
  • Patent number: 7565044
    Abstract: An optical module with a first optical waveguide substrate having end faces; a second optical waveguide substrate which includes a first optical waveguide, a second optical waveguide, and end faces, the second optical waveguide substrate having an opening between the first optical waveguide and the second optical waveguide; and a first deflection device which is mounted in the opening, wherein one of the end faces of the first optical waveguide substrate and one of the end faces of the second optical waveguide substrate are coupled to each other.
    Type: Grant
    Filed: February 20, 2008
    Date of Patent: July 21, 2009
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Akahoshi, Akio Sugama, Shigenori Aoki
  • Patent number: 7522788
    Abstract: An optical module with a plurality of optical waveguide substrates having element mounting openings and end surfaces which are adhered to each other with an optical adhesive; and a plurality of light deflecting element arrays mounted to the respective element mounting openings of the plurality of optical waveguide substrates, the plurality of light deflecting element arrays including a plurality of light deflecting elements.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: April 21, 2009
    Assignee: Fujitsu Limited
    Inventors: Tomoyuki Akahoshi, Akio Sugama, Shigenori Aoki