Abstract: A method of manufacturing a semiconductor device having a process for cleaning a semiconductor substrate after the semiconductor substrate is etched for patterning includes a first process of preparing the semiconductor substrate having a first temperature, a second process of setting the semiconductor substrate at a second temperature, a third process of etching the semiconductor substrate having the second temperature by etching liquid having a third temperature, a fourth process of cleaning the semiconductor substrate to which the etching liquid is adhered, by ultrapure water having a fourth temperature, wherein the second temperature is set at the range between the first and the third temperatures.

Abstract: A semiconductor device manufacturing method includes: providing a laminated member in which at least a first GaAs layer, an InAlGaAs layer and a second GaAs layer are laminated on or above a substrate in this order; and etching the second GaAs layer using the InAlGaAs layer as an etching stopper layer. A ratio of In:Al of the InAlGaAs layer is in a range of approximately 4:6 to approximately 6:4 and a ratio of (In+Al):Ga of the InAlGaAs layer is in a range of approximately 1.5:8.5 to approximately 5:5.

Abstract: A field effect transistor having a double recess structure, which minimizes an influence exerted on a channel region depending upon the surface state of an outer recess section. In the field effect transistor having such a double recess structure, an ohmic contact layer at the surface of the outer recess section is made to have a thickness so as to be in a to completely depleted state.

Abstract: A semiconductor device manufacturing method includes: providing a laminated member in which at least a first GaAs layer, an InAlGaAs layer and a second GaAs layer are laminated on or above a substrate in this order; and etching the second GaAs layer using the InAlGaAs layer as an etching stopper layer. A ratio of In:Al of the InAlGaAs layer is in a range of approximately 4:6 to approximately 6:4 and a ratio of (In+Al):Ga of the InAlGaAs layer is in a range of approximately 1.5:8.5 to approximately 5:5.

Abstract: The semiconductor device (10) comprises a semiinsulating substrate (12), a layered structure (20) of compound semiconductor which is a mesa structure (18) and contains an active channel layer (14), a first and a second metal main electrodes (22a, 22b) which are provided on the layered structure (20), a first and a second ion implantation regions (40a, 40b) which are provided at the depth level below the active channel layer, and a metal control electrode (26) which is provided along the channel width direction from the first ion implantation region to the second ion implantation region, crossing over the upper side of the active channel layer.

Abstract: A method of manufacturing a semiconductor device having a process for cleaning a semiconductor substrate after the semiconductor substrate is etched for patterning includes a first process of preparing the semiconductor substrate having a first temperature, a second process of setting the semiconductor substrate at a second temperature, a third process of etching the semiconductor substrate having the second temperature by etching liquid having a third temperature, a fourth process of cleaning the semiconductor substrate to which the etching liquid is adhered, by ultrapure water having a fourth temperature, wherein the second temperature is set at the range between the first and the third temperatures.

Abstract: The present invention provides a field effect transistor having a double recess structure, which minimizes an influence exerted on a channel region depending upon the surface state of an outer recess section. In the field effect transistor having such a double recess structure, an ohmic contact layer at the surface of the outer recess section is made thick to deplete the ohmic contact layer completely.

Abstract: The semiconductor device (10) comprises a semiinsulating substrate (12), a layered structure (20) of compound semiconductor which is a mesa structure (18) and contains an active channel layer (14), a first and a second metal main electrodes (22a, 22b) which are provided on the layered structure (20), a first and a second ion implantation regions (40a, 40b) which are provided at the depth level below the active channel layer, and a metal control electrode (26) which is provided along the channel width direction from the first ion implantation region to the second ion implantation region, crossing over the upper side of the active channel layer.