Abstract: A server stores multiple configuration data which respectively provide different functions to a test system. A tester hardware is configured to be capable of changing at least a part of its functions according to the configuration data stored in nonvolatile memory included in the tester hardware. A control program is installed on an information processing apparatus. The control program provides the information processing apparatus with (i) a function of displaying multiple configuration data candidates on a display when the test system is set up, and (ii) a function of writing the configuration data selected by the user to the nonvolatile memory of the tester hardware.

Abstract: A high-strength brass alloy for sliding members, consists of, by mass %, 17 to 28% of Zn, 5 to 10% of Al, 4 to 10% of Mn, 1 to 5% of Fe, 0.1 to 3% of Ni, 0.5 to 3% of Si, and the balance of Cu and inevitable impurities. The high-strength brass alloy has a structure that includes a matrix of a single phase structure of the ? phase and includes at least one of Fe—Mn—Si intermetallic compounds in the form of aciculae, spheres, or petals dispersed in the ? phase.

Abstract: A server stores multiple configuration data which respectively provide different functions to a test system. A tester hardware is configured to be capable of changing at least a part of its functions according to the configuration data stored in nonvolatile memory included in the tester hardware. A control program is installed on an information processing apparatus. The control program provides the information processing apparatus with (i) a function of displaying multiple configuration data candidates on a display when the test system is set up, and (ii) a function of writing the configuration data selected by the user to the nonvolatile memory of the tester hardware.

Abstract: In a multilayered sintered sliding member, a porous sintered alloy layer comprising 3 to 10 wt. % of an Sn component, 10 to 30 wt. % of an Ni component, 0.5 to 4 wt. % of a P component, 30 to 50 wt. % of an Fe component, 1 to 10 wt. % of a high-speed tool steel component, 1 to 5 wt. % of a graphite component, and 20 to 55 wt. % of a copper component is integrally diffusion-bonded to a backing plate.

Abstract: A high-strength brass alloy for sliding members, consists of, by mass %, 17 to 28% of Zn, 5 to 10% of Al, 4 to 10% of Mn, 1 to 5% of Fe, 0.1 to 3% of Ni, 0.5 to 3% of Si, and the balance of Cu and inevitable impurities. The high-strength brass alloy has a structure that includes a matrix of a single phase structure of the ? phase and includes at least one of Fe—Mn—Si intermetallic compounds in the form of aciculae, spheres, or petals dispersed in the ? phase.

Abstract: In a multilayered sintered sliding member, a porous sintered alloy layer comprising 3 to 10 wt. % of an Sn component, 10 to 30 wt. % of an Ni component, 0.5 to 4 wt. % of a P component, 30 to 50 wt. % of an Fe component, 1 to 10 wt. % of a high-speed tool steel component, 1 to 5 wt. % of a graphite component, and 20 to 55 wt. % of a copper component is integrally diffusion-bonded to a backing plate.

Abstract: There is provided a measuring apparatus that generates a first strobe signal and a second strobe signal in synchronization with an output signal, sequentially changes phases of the strobe signals whenever the electronic device outputs the output signal multiple times, acquires a signal level of the output signal at each phase of the strobe signals by the multiple times, counts the number of times by which the signal level of the output signal to the first strobe signal is a High level for each phase of the first strobe signal, counts the number of times by which the signal level of the output signal to the second strobe signal is a Low level for each phase of the second strobe signal, and computes a phase of a variation point of a waveform of the output signal, a jitter amount, and distribution of jitter based on the counted number of times. The measuring apparatus measures a variation point of a waveform of the output signal, a jitter amount, and distribution of jitter by one-time test.

Abstract: There is disclosed a semiconductor memory test apparatus capable of easily generating an address to be input into a failure analysis memory for testing a memory device having a burst function which automatically generates addresses for banks therein. Each of registers corresponding to the banks of the memory device holds a line address of the corresponding bank. When a start address of one of the banks is input to the memory device, a line address of the same bank as the start address is read out from the register corresponding to the bank and output to a failure analysis memory together with the start address. Furthermore, during burst operation of the bank, the registers output the line address to the failure analysis memory together the same line address as the memory device generated by calculating the start address for each clock cycle.

Abstract: There is provided a measuring apparatus that generates a first strobe signal and a second strobe signal in synchronization with an output signal, sequentially changes phases of the strobe signals whenever the electronic device outputs the output signal multiple times, acquires a signal level of the output signal at each phase of the strobe signals by the multiple times, counts the number of times by which the signal level of the output signal to the first strobe signal is a High level for each phase of the first strobe signal, counts the number of times by which the signal level of the output signal to the second strobe signal is a Low level for each phase of the second strobe signal, and computes a phase of a variation point of a waveform of the output signal, a jitter amount, and distribution of jitter based on the counted number of times. The measuring apparatus measures a variation point of a waveform of the output signal, a jitter amount, and distribution of jitter by one-time test.

Abstract: There is disclosed a semiconductor memory test apparatus capable of easily generating an address to be input into a failure analysis memory for testing during interleave operation of a memory device having a burst function between banks. Each of the registers corresponding to DUT banks holds a line address of the corresponding bank. When a start row address of one of the banks is input to the DUT, a line address of the same bank as the start row address is read out from the register corresponding to the bank and output to a failure analysis memory together with the start row address. Furthermore, during burst operation of the bank, it is possible to output the line address to the failure analysis memory together the same row address as the memory device generated by calculating the start row address for each clock cycle.