Patents by Inventor Tong-Jyun Huang

Tong-Jyun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10121881
    Abstract: A semiconductor device preferably includes a substrate, a fin-shaped structure on the substrate, a buffer layer on the fin-shaped structure, and an epitaxial layer on the buffer layer. Preferably, the buffer layer is made of silicon germanium and including three or more than three elements. The buffer layer also includes dopants selected from the group consisting of P, As, Sb, Bi, C, and F.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: November 6, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Yi-Fan Li, Kun-Hsin Chen, Tong-Jyun Huang, Jyh-Shyang Jenq, Nan-Yuan Huang
  • Patent number: 10090398
    Abstract: A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of each of the sacrificial features, wherein all of the spacers are arranged to have a layout pattern; and transferring the layout pattern to the target layer so as to form a first feature and a second feature, wherein the first feature comprises a vertical segment and a horizontal segment, the second feature comprises a vertical segment and a horizontal segment, and a distance between the vertical segment of the first feature and the vertical segment of the second feature is less than a minimum feature size generated by an exposure apparatus.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: October 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Rai-Min Huang, I-Ming Tseng, Tong-Jyun Huang, Kuan-Hsien Li
  • Publication number: 20180108656
    Abstract: An asymmetrical fin structure includes a substrate. The substrate includes a top surface. A fin element extends from the substrate and connects to the substrate. The fin element includes two sidewalls respectively disposed at two opposite sides of the fin element. The sidewalls contact the top surface of the substrate. An epitaxial layer contacts and only covers one of the sidewalls. The other sidewall on the fin element does not contact any epitaxial layer.
    Type: Application
    Filed: November 10, 2016
    Publication date: April 19, 2018
    Inventors: Chao-Hung Lin, Tong-Jyun Huang, Shih-Hung Tsai, Jyh-Shyang Jenq
  • Patent number: 9859147
    Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: January 2, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Jyun Huang, Rai-Min Huang, I-Ming Tseng, Kuan-Hsien Li, Chen-Ming Huang
  • Patent number: 9842760
    Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate having a fin-shaped structure thereon is provided, a spacer is formed adjacent to the fin-shaped structure, and the spacer is used as mask to remove part of the substrate for forming an isolation trench, in which the isolation trench includes two sidewall portions and a bottom portion. Next, a plasma doping process is conducted to implant dopants into the two sidewall portions and the bottom portion of the isolation trench.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: December 12, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Tong-Jyun Huang, Shih-Hung Tsai, Jyh-Shyang Jenq, Chun-Yao Yang, Ming-Shiou Hsieh, Rong-Sin Lin
  • Publication number: 20170338227
    Abstract: A semiconductor device includes at least a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 23, 2017
    Inventors: Li-Wei Feng, Tong-Jyun Huang, Shih-Hung Tsai, Jia-Rong Wu, Tien-Chen Chan, Yu-Shu Lin, Jyh-Shyang Jenq
  • Patent number: 9825144
    Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.
    Type: Grant
    Filed: July 10, 2017
    Date of Patent: November 21, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shih-Fang Tzou, Chien-Ming Lai, Yi-Wen Chen, Hung-Yi Wu, Tong-Jyun Huang, Chien-Ting Lin, Chun-Hsien Lin
  • Publication number: 20170309722
    Abstract: A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.
    Type: Application
    Filed: July 10, 2017
    Publication date: October 26, 2017
    Inventors: Shih-Fang Tzou, Chien-Ming Lai, Yi-Wen Chen, Hung-Yi Wu, Tong-Jyun Huang, Chien-Ting Lin, Chun-Hsien Lin
  • Publication number: 20170309727
    Abstract: A method of fabricating a patterned structure of a semiconductor device includes the following steps: providing a substrate having a target layer thereon; forming a patterned sacrificial layer on the target layer, wherein the patterned sacrificial layer consists of a plurality of sacrificial features; forming spacers respectively on sidewalls of each of the sacrificial features, wherein all of the spacers are arranged to have a layout pattern; and transferring the layout pattern to the target layer so as to form a first feature and a second feature, wherein the first feature comprises a vertical segment and a horizontal segment, the second feature comprises a vertical segment and a horizontal segment, and a distance between the vertical segment of the first feature and the vertical segment of the second feature is less than a minimum feature size generated by an exposure apparatus.
    Type: Application
    Filed: July 12, 2017
    Publication date: October 26, 2017
    Inventors: Rai-Min Huang, I-Ming Tseng, Tong-Jyun Huang, Kuan-Hsien Li
  • Publication number: 20170263732
    Abstract: A semiconductor device preferably includes a substrate, a fin-shaped structure on the substrate, a buffer layer on the fin-shaped structure, and an epitaxial layer on the buffer layer. Preferably, the buffer layer is made of silicon germanium and including three or more than three elements. The buffer layer also includes dopants selected from the group consisting of P, As, Sb, Bi, C, and F.
    Type: Application
    Filed: April 6, 2017
    Publication date: September 14, 2017
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Yi-Fan Li, Kun-Hsin Chen, Tong-Jyun Huang, Jyh-Shyang Jenq, Nan-Yuan Huang
  • Patent number: 9754938
    Abstract: A semiconductor device includes a substrate, fin-shaped structures, a protection layer, epitaxial layers, and a gate electrode. The fin-shaped structures are disposed in a first region and a second region of the substrate. The protection layer conformally covers the surface of the substrate and the sidewalls of fin-shaped structures. The epitaxial layers respectively conformally and directly cover the fin-shaped structures in the first region. The gate electrode covers the fin-shaped structures in the second region, and the protection layer is disposed between the gate electrode and the fin-shaped structures.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: September 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Tong-Jyun Huang, Shih-Hung Tsai, Jia-Rong Wu, Tien-Chen Chan, Yu-Shu Lin, Jyh-Shyang Jenq
  • Patent number: 9755048
    Abstract: A patterned structure of a semiconductor device includes a substrate, a first feature and a second feature. The first feature and the second feature are disposed on the substrate, and either of which includes a vertical segment and a horizontal segment. There is a distance between the vertical segment of the first feature and the vertical segment of the second feature, and the distance is less than the minimum exposure limits of an exposure apparatus.
    Type: Grant
    Filed: May 13, 2015
    Date of Patent: September 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Rai-Min Huang, I-Ming Tseng, Tong-Jyun Huang, Kuan-Hsien Li
  • Patent number: 9653603
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a recess in the substrate; forming a buffer layer in the recess; forming an epitaxial layer on the buffer layer; and removing part of the epitaxial layer, part of the buffer layer, and part of the substrate to form fin-shaped structures.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 16, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Li-Wei Feng, Shih-Hung Tsai, Yi-Fan Li, Kun-Hsin Chen, Tong-Jyun Huang, Jyh-Shyang Jenq, Nan-Yuan Huang
  • Publication number: 20170047244
    Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 16, 2017
    Inventors: Tong-Jyun Huang, Rai-Min Huang, I-Ming Tseng, Kuan-Hsien Li, Chen-Ming Huang
  • Patent number: 9552978
    Abstract: A method of decreasing fin bending, includes providing a substrate including a plurality of fins, wherein a plurality of trenches are defined by the fins, the trenches include a first trench and a second trench, and the second trench is wider than the first trench. Later, a flowable chemical vapor deposition process is performed to form a silicon oxide layer covering the fins, filling up the first trench and partially filling in the second trench. After that, the silicon oxide layer is solidified by a UV curing process. Finally, after the UV curing process, the silicon oxide layer is densified by a steam anneal process.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: January 24, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Jyun Huang, Li-Wei Feng, Shih-Hung Tsai, Jyh-Shyang Jenq, Chien-Ting Lin
  • Patent number: 9524909
    Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: December 20, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tong-Jyun Huang, Rai-Min Huang, I-Ming Tseng, Kuan-Hsien Li, Chen-Ming Huang
  • Patent number: 9490342
    Abstract: A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: November 8, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Yi-Wen Chen, Zhi-Cheng Lee, Tong-Jyun Huang, Che-Hua Hsu, Kun-Hsien Lin, Tzung-Ying Lee, Chi-Mao Hsu, Hsin-Fu Huang, Chin-Fu Lin
  • Patent number: 9466691
    Abstract: A fin shaped structure and a method of forming the same, wherein the method includes forming a fin structure on a substrate. Next, an insulation layer is formed on the substrate and surrounds the fin structure, wherein the insulation layer covers a bottom portion of the fin structure to expose an exposed portion of the fin structure protruded from the insulation layer. Then, a buffer layer is formed on the fin structure. Following this, a threshold voltage implantation process is performed to penetrate through the buffer layer after forming the insulation layer, to form a first doped region on the exposed portion of the fin structure.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: October 11, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: I-Ming Tseng, Rai-Min Huang, Tong-Jyun Huang, Kuan-Hsien Li, Chen-Ming Huang
  • Publication number: 20160293491
    Abstract: A fin structure cutting process includes the following steps. Four fin structures are formed in a substrate, where the four fin structures including a first fin structure, a second fin structure, a third fin structure and a fourth fin structure are arranged sequentially and parallel to each other. A first fin structure cutting process is performed to remove top parts of the second fin structure and the third fin structure, thereby a first bump being formed from the second fin structure, and a second bump being formed from the third fin structure. A second fin structure cutting process is performed to remove the second bump and the fourth fin structure completely, but to preserve the first bump beside the first fin structure. Moreover, the present invention provides a fin structure formed by said process.
    Type: Application
    Filed: April 27, 2015
    Publication date: October 6, 2016
    Inventors: Tong-Jyun Huang, Rai-Min Huang, I-Ming Tseng, Kuan-Hsien Li, Chen-Ming Huang
  • Publication number: 20160293726
    Abstract: A patterned structure of a semiconductor device includes a substrate, a first feature and a second feature. The first feature and the second feature are disposed on the substrate, and either of which includes a vertical segment and a horizontal segment. There is a distance between the vertical segment of the first feature and the vertical segment of the second feature, and the distance is less than the minimum exposure limits of an exposure apparatus.
    Type: Application
    Filed: May 13, 2015
    Publication date: October 6, 2016
    Inventors: Rai-Min Huang, I-Ming Tseng, Tong-Jyun Huang, Kuan-Hsien Li