Patents by Inventor Toru Iwata

Toru Iwata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090106460
    Abstract: An object of the present invention is to provide a technique to improve the data transmission efficiency which allows correct reception of the data at the same time.
    Type: Application
    Filed: February 20, 2007
    Publication date: April 23, 2009
    Inventors: Hiroshi Suenaga, Osamu Shibata, Noriaki Takeda, Toru Iwata, Takaharu Yoshida, Yoshiyuki Saito
  • Publication number: 20090086852
    Abstract: The data receiver device includes: a bit phase synchronizing circuit (10) for performing phase adjustment of a received data signal to set a predetermined phase relationship between the data signal and a corresponding clock signal; and a state detection circuit (20) for outputting a detection signal once detecting that the data signal inputted into the bit phase synchronizing circuit (10) is in a stable state based on a data signal phase-adjusted by the bit phase synchronizing circuit (10) and a corresponding clock signal. The bit phase synchronizing circuit (10) initializes the phase adjustment of the data signal when receiving the detection signal.
    Type: Application
    Filed: July 10, 2006
    Publication date: April 2, 2009
    Inventors: Hirokazu Sugimoto, Toru Iwata
  • Patent number: 7480548
    Abstract: It is an object of the present invention to solve the problem of a drop in precision in conventional systems using a square pyramid type five-hole probe due to the drop in atmospheric pressure in high altitude ranges, and to provide a wide velocity range flight velocity vector measurement system that can prevent a drop in measurement precision. Furthermore, it is also an object of the present invention to provide a method for eliminating the effects of detection fluctuations caused by adhering water droplets, ice particles or dust in a wide velocity range flight velocity vector measurement system.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: January 20, 2009
    Assignees: Japan Aerospace Exploration Agency, Fuji Heavy Industries Ltd., Tokyo Aircraft Instrument Co., Ltd.
    Inventors: Masashi Shigemi, Akira Koike, Makoto Ueno, Tomonari Hirotani, Teruomi Nakaya, Hiroshi Wakai, Toru Iwata
  • Publication number: 20080315911
    Abstract: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.
    Type: Application
    Filed: April 11, 2008
    Publication date: December 25, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Tsuyoshi Ebuchi, Toru Iwata, Takefumi Yoshikawa
  • Publication number: 20080303567
    Abstract: A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
    Type: Application
    Filed: February 19, 2008
    Publication date: December 11, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Shiro SAKIYAMA, Yusuke Tokunaga, Shiro Dosho, Toru Iwata, Takashi Hirata, Hideki Yoshii, Yasuyuki Doi, Makoto Hattori
  • Patent number: 7453313
    Abstract: A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: November 18, 2008
    Assignee: Panasonic Corporation
    Inventors: Shiro Sakiyama, Yusuke Tokunaga, Shiro Dosho, Toru Iwata, Takashi Hirata
  • Publication number: 20080247492
    Abstract: In a signal receiving circuit including a plurality of input channels, there are provided N input detection circuits 2a to 2n for receiving clock signals S1-c to SN-c included in N channels of signals S1 to SN. Each of the input detection circuits 2a to 2n detects the transition of the input signal of the corresponding channel and further confirms that the signal of the corresponding channel is being received after the transition detection to thereby detect the input of the signal of the corresponding channel. If one of the input detection circuits 2a to 2n detects the input of the signal of the corresponding channel, the selection circuit 3 selects and outputs the clock signal and the data signal in the signal of the channel of which the input is detected. The selected output signal is successively subjected to input processes through one each of the phase synchronization circuit 4, the serial/parallel conversion circuit 5, etc., which are shared by N channels.
    Type: Application
    Filed: February 1, 2005
    Publication date: October 9, 2008
    Inventors: Hirokazu Sugimoto, Toru Iwata
  • Patent number: 7397268
    Abstract: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: July 8, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsuyoshi Ebuchi, Toru Iwata, Takefumi Yoshikawa
  • Publication number: 20070183175
    Abstract: A charge pumping circuit includes a first switch for controlling one of push and pull operations in accordance with a first control signal; a current mirror circuit constructed from transistors each having a different polarity from the first switch; a second switch for controlling current input to the current mirror circuit in accordance with a second control signal, the second switch being constructed from a transistor having the same characteristic as a transistor used for constructing the first switch; a first MOS capacitor one end of which is connected to an input side of the current mirror circuit; a second MOS capacitor receiving, at one end thereof, a current concerned with the push and pull operations; and a voltage buffer connected to the first and second MOS capacitors. The other of the push and pull operations is performed with an output current of the current mirror circuit.
    Type: Application
    Filed: December 13, 2006
    Publication date: August 9, 2007
    Inventors: Shiro Sakiyama, Yusuke Tokunaga, Shiro Dosho, Toru Iwata, Takashi Hirata
  • Patent number: 7242733
    Abstract: The clock recovery circuit includes a first oscillator and an edge detector. The first oscillator generates a plurality of clocks having different phases and a predetermined frequency. The edge detector detects two clocks, among the plurality of clocks, between edges of which an input data signal has made a transition. The first oscillator includes a plurality of delay cells connected in a ring, and outputs of the plurality of delay cells are output as the plurality of clocks. Each of the plurality of delay cells selectively delays a first-delay added input data signal or the signal output from the preceding delay cell, and outputs the selected delayed signal. The edge detector controls one delay cell among the plurality of delay cells corresponding to the result of the detection, to delay and output the first-delay added input data signal.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: July 10, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Toru Iwata
  • Publication number: 20070115025
    Abstract: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.
    Type: Application
    Filed: January 16, 2007
    Publication date: May 24, 2007
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsuyoshi Ebuchi, Toru Iwata, Takefumi Yoshikawa
  • Patent number: 7212028
    Abstract: First and second transmission lines and are connected to each other in series. A first terminator is connected to the first transmission line in parallel, and is provided externally of a semiconductor device. A second terminator is connected to the second transmission line in parallel, and is provided inside the semiconductor device. The values of the first and second terminator are adjusted so that the combined resistance value of first and second terminator and the second transmission line matches with the impedance of the first transmission line. Impedance matching of the entire transmission line can be achieved with this simple construction, thus, a stable, high quality signal can be transmitted.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: May 1, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Osamu Shibata, Toru Iwata, Yoshiyuki Saito, Satoshi Takahashi, Wataru Itoh
  • Patent number: 7204096
    Abstract: An air discharge outlet comprises line air discharge outlets (35) and corner air discharge outlets (36). The line air discharge outlets (35) are so formed as to extend, respectively, along four sides of a casing bottom part having four side parts and four corner parts wherein the side and corner parts are formed in contiguous relationship to one another. The corner air discharge outlets (36) are formed, respectively, in the four casing corner parts so that each corner air discharge outlet (36) establishes connection between adjacent ones of the line air discharge outlets (35). And, each line air discharge outlet (35) is provided with a swing vane (38) swingable about a longitudinal shaft (41) of each line air discharge outlet (35). Each corner air discharge outlet (36) is provided with a fixed stationary vane (39).
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: April 17, 2007
    Assignee: Daikin Industries, Ltd.
    Inventors: Toru Iwata, Masakazu Hirai
  • Publication number: 20070080728
    Abstract: A phase adjustment circuit for discretely adjusting a phase of a data signal and that of a clock signal, the phase adjustment circuit including: a delay line for delaying the clock signal to produce a delayed clock signal; a phase comparator for comparing the phase of the data signal with that of the delayed clock signal; a delay control section for outputting a delay control signal based on the comparison result from the phase comparator; and a delay control section for outputting a delay control signal based on a frequency of the clock signal. The delay line determines a delay amount of the delayed clock signal with respect to the clock signal based on the control signals.
    Type: Application
    Filed: August 31, 2006
    Publication date: April 12, 2007
    Inventor: Toru Iwata
  • Publication number: 20070041483
    Abstract: A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.
    Type: Application
    Filed: October 26, 2006
    Publication date: February 22, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Toru Iwata, Hiroyuki Yamauchi, Takefumi Yoshikawa
  • Patent number: 7176708
    Abstract: In a receiver circuit that receives data and clock signals through the cables, the number of transitions of a signal obtained based on the data or clock signal is detected by a frequency detection circuit, and when the number of transitions is not more than a predetermined set value, a signal for resetting the operation of a serial-parallel converter circuit included in a data processing unit is output, so as to control the output of received data. Thus, disconnection of the cable can be detected with low power consumption without providing a pull-up resistor and pull-down resistor and noise resistance can be improved.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: February 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tsuyoshi Ebuchi, Toru Iwata, Takefumi Yoshikawa
  • Patent number: 7136441
    Abstract: A driver and a receiver supply a data signal, which is based on serial data having a regular bit pattern, such as a clock, which includes 1's and 0's alternating with each other during an adjustment period, and is based on serial data having an arbitrary bit pattern during a transfer period following the adjustment period. A duty factor controller adjusts a data transition characteristic of the driver or the receiver so that a duty factor of the data signal supplied from the receiver is equal to 50% in the adjustment period, and has the adjusted data transition characteristic stored. A clock recovery unit recovers a clock synchronized with a data signal, which is supplied from the receiver in the transfer period and is based on the adjusted transition characteristic, from the data signal.
    Type: Grant
    Filed: January 8, 2002
    Date of Patent: November 14, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toru Iwata, Hiroyuki Yamauchi, Takefumi Yoshikawa
  • Publication number: 20060194137
    Abstract: It is contemplated to provide irregular shaped ferrite carrier which has a lower resistance, a high specific surface area, a low specific gravity and a longer operational life, and an electrophotographic developer comprising the ferrite carrier which prevents the toner scattering, has a high image density, and is responsive to high-speed and color imaging. The irregular shaped ferrite carrier is characterized in that the carrier particles are irregular shaped, and 40 percent by number or more of the particles have a rock candy sugar shape and/or an oyster shell shape, and that the shape factor (SF-1=R2/S×?/4×100, wherein R is a maximum length and S is a projected area.) is 140 to 250, and the distribution width (?) is 60 or less.
    Type: Application
    Filed: February 28, 2006
    Publication date: August 31, 2006
    Applicant: POWDERTECH CO., LTD.
    Inventors: Hiromichi Kobayashi, Toru Iwata, Toshio Honjo
  • Publication number: 20060178790
    Abstract: It is an object of the present invention to solve the problem of a drop in precision in conventional systems using a square pyramid type five-hole probe due to the drop in atmospheric pressure in high altitude ranges, and to provide a wide velocity range flight velocity vector measurement system that can prevent a drop in measurement precision. Furthermore, it is also an object of the present invention to provide a method for eliminating the effects of detection fluctuations caused by adhering water droplets, ice particles or dust in a wide velocity range flight velocity vector measurement system.
    Type: Application
    Filed: September 13, 2005
    Publication date: August 10, 2006
    Applicants: JAPAN AEROSPACE EXPLORATION AGENCY, FUJI HEAVY INDUSTRIES LTD., TOKYO AIRCRAFT INSTRUMENT CO., LTD.
    Inventors: Masashi Shigemi, Akira Koike, Makoto Ueno, Tomonari Hirotani, Teruomi Nakaya, Hiroshi Wakai, Toru Iwata
  • Publication number: 20060176091
    Abstract: A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and falling of the reference clock signal and a transition of the delayed clock signal. A charge pump circuit performs on the loop filter, according to these two signals, a push (or pull) operation during an interval extending from a rising (or falling) of the reference clock signal to the transition of the delayed clock signal and a pull (or push) operation during an interval extending from the transition of the delayed clock signal to a falling (or rising) of the reference clock signal.
    Type: Application
    Filed: November 30, 2005
    Publication date: August 10, 2006
    Inventors: Shiro Sakiyama, Yusuke Tokunaga, Shiro Dosho, Toru Iwata, Takashi Hirata, Hideki Yoshii, Yasuyuki Doi, Makoto Hattori