Patents by Inventor Toru Katagiri

Toru Katagiri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11336305
    Abstract: A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: May 17, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Kenji Funaoka, Takuya Haga, Toru Katagiri, Konosuke Watanabe
  • Publication number: 20220043920
    Abstract: A method may include publishing metadata to a blockchain, the metadata describing a training task associated with a global machine-learning model and computational resource requirements for performing the training task. The method may include receiving a request to participate in training the global machine-learning model from one or more clients based on a relevance of a respective local dataset of each of the clients to the training task and a suitability of the clients to the computational resource requirements for performing the training task. The method may include obtaining local model updates in which each respective local model corresponds to a respective client and each respective local model update is generated based on training the global machine-learning model with each of the local datasets. The method may include aggregating the plurality of local model updates and generating an updated global machine-learning model based on the aggregated local model update.
    Type: Application
    Filed: June 24, 2021
    Publication date: February 10, 2022
    Inventors: Qiong ZHANG, Paparao PALACHARLA, Junichi SUGA, Toru KATAGIRI, Tadashi IKEUCHI, Motoyoshi SEKIYA
  • Publication number: 20220044162
    Abstract: A method may include publishing metadata to a blockchain, the metadata describing a training task associated with a global machine-learning model and computational resource requirements for performing the training task. The method may include receiving a request to participate in training the global machine-learning model from one or more clients based on a relevance of a respective local dataset of each of the clients to the training task and a suitability of the clients to the computational resource requirements for performing the training task. The method may include obtaining local model updates in which each respective local model corresponds to a respective client and each respective local model update is generated based on training the global machine-learning model with each of the local datasets. The method may include aggregating the plurality of local model updates and generating an updated global machine-learning model based on the aggregated local model update.
    Type: Application
    Filed: June 24, 2021
    Publication date: February 10, 2022
    Inventors: Qiong ZHANG, Paparao PALACHARLA, Tadashi IKEUCHI, Motoyoshi SEKIYA, Junichi SUGA, Toru KATAGIRI
  • Publication number: 20220027092
    Abstract: A memory system includes a non-volatile memory and a controller. The controller controls writing of data to the non-volatile memory or reading of data from the non-volatile memory, in response to a command from at least one host. The controller performs command fetching by calculating for each of a plurality of queues, a remaining processing amount, which is an amount of processing remaining for one or more commands previously fetched therefrom, selecting a queue based on the remaining processing amounts calculated for the plurality of queues, and fetching a new command from the selected queue.
    Type: Application
    Filed: February 26, 2021
    Publication date: January 27, 2022
    Inventor: Toru KATAGIRI
  • Patent number: 11063767
    Abstract: An apparatus serves as a node device included in a distributed data sharing network, and shares, by using a blockchain, a piece of event information related to an event generated in a terminal, among node devices included in the distributed data sharing network, where the blockchain is a continuously growing list of blocks which are linked and secured using cryptography. The apparatus generates a piece of event data including the piece of event information related to the event, and causes the generated piece of event data to be stored in one of the node devices included in the distributed data sharing network.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: July 13, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Satoshi Imai, Toru Katagiri, Motoyoshi Sekiya
  • Patent number: 10848840
    Abstract: A communication apparatus includes a receiver configured to receive a signal from a first line, a signal processing circuit configured to perform descrambling processing on the received signal, detect a control signal from the descrambled signal, generate a signal in which an idle signal in accordance with a difference amount between a communication capacity of a second line as a transmission destination and a communication capacity of the first line is inserted in a position where the control signal is detected, and perform scrambling processing on the generated signal, and a transmitter configured to output the scrambled signal to the second line.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: November 24, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yuji Tochio, Toru Katagiri, Hiroshi Tomonaga
  • Publication number: 20200350929
    Abstract: A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.
    Type: Application
    Filed: July 22, 2020
    Publication date: November 5, 2020
    Inventors: Kenji FUNAOKA, Takuya HAGA, Toru KATAGIRI, Konosuke WATANABE
  • Patent number: 10763897
    Abstract: A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: September 1, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kenji Funaoka, Takuya Haga, Toru Katagiri, Konosuke Watanabe
  • Patent number: 10708239
    Abstract: An edge server disposed on an edge of a cloud network, includes: a processor, wherein when encryption key information relating to a terminal which requests a connection to the edge server and the encryption key information generated before the request, is included in shared information shared between a cloud server and another edge server in the cloud network, the processor is configured to start encryption communication with the terminal using the encryption key information of the shared information.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: July 7, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Satoshi Imai, Motoyoshi Sekiya, Toru Katagiri, Tetsuya Yamada
  • Patent number: 10698296
    Abstract: Provided is an interchangeable lens including: a lens position detection unit configured to detect a position of a lens; a motor configured to move a movable lens frame to which the lens is fixed; a driving state detection unit configured to detect a driving state of the motor; and a control unit configured to decide a driving speed of the motor based on a difference between a target speed, which is based on a difference between a target position of the lens acquired from an imaging device and the position of the lens detected by the lens position detection unit, and a speed according to the driving state detected by the driving state detection unit.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: June 30, 2020
    Assignee: Sony Corporation
    Inventors: Tomoomi Ito, Toru Katagiri
  • Patent number: 10459846
    Abstract: According to one embodiment, a memory system is connectable to a host device including a first memory. The memory system includes a memory controller and a second memory in which data from a host device is stored. The memory controller includes a third memory, a first unit and a second unit and has a first space. The first unit designates a first address in the first space. The second unit converts, by using a conversion table, the first address into a second address in a first area of the first memory. The conversion table includes a plurality of layers and includes a first conversion table of a top layer and a second conversion table of a layer lower than the first conversion table. The first conversion table is stored in the third memory. The second conversion table is stored in a second area of the first memory.
    Type: Grant
    Filed: March 9, 2016
    Date of Patent: October 29, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yukimasa Miyamoto, Toru Katagiri, Shoji Sawamura
  • Patent number: 10305588
    Abstract: There is provided a network management device including a memory in which a change rate of a transmission quality of a first optical signal to be transmitted on a first path with respect to a power of the first optical signal is stored, and a processor coupled to the memory and the processor configured to determine, based on the change rate, whether to set a second path on which a second optical signal transmits to overlap with at least a portion of a route of the first path.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: May 28, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Masatake Miyabe, Toru Katagiri
  • Publication number: 20190089383
    Abstract: A memory system, which is connectable to a host, includes a non-volatile memory and a controller configured to store data in the non-volatile memory and in a memory region within the host and read the data from the memory region within the host. The controller includes a first encoding/decoding circuit configured to execute encoding/decoding with a first encoding scheme, a second encoding/decoding circuit configured to execute encoding/decoding with a second encoding scheme having a higher error correcting capability than an error correcting capability of the first encoding scheme, an encoding scheme selecting circuit configured to select an encoding/decoding circuit from the first encoding/decoding circuit and the second encoding/decoding circuit to perform encoding of data to be stored in the memory region, based on information about the data read from the memory region.
    Type: Application
    Filed: March 1, 2018
    Publication date: March 21, 2019
    Inventors: Kenji FUNAOKA, Takuya HAGA, Toru KATAGIRI, Konosuke WATANABE
  • Patent number: 10230462
    Abstract: An optical transmission characteristic measurement method includes starting transmission of an optical signal from a transmitting node to a receiving node; receiving a bit error rate value measured by the receiving node and relates to the optical signal; determining whether the bit error rate value is higher than a given threshold; adjusting input power of the optical signal to lower until it is determined that the bit error rate value is higher than the given threshold when it is determined that the bit error rate value is not higher than the given threshold; estimating an optical signal to noise ratio from the bit error rate value when it is determined that the bit error rate value is higher than the given threshold; and calculating an optical signal to noise ratio based on the estimated optical signal to noise ratio and an amount of lowering of the input power.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: March 12, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Shoichiro Oda, Toru Katagiri, Satoru Okano, Masatake Miyabe, Yasuhiko Aoki
  • Patent number: 10158422
    Abstract: There is provided an apparatus configured to estimate optical transmission performance in a transmission path of an optical signal, the apparatus including a memory, and a processor coupled to the memory and the processor configured to acquire a first index related to a first transmission performance of an optical signal transmitted through a span group between a first node and an n-th node and a second index related to a second transmission performance of an optical signal transmitted through a span or a span group between the first node and an m-th node, wherein n is an integer of 3 or more, and m is the integer satisfying m<n, and estimate a third index related to a third transmission performance of an optical signal to be transmitted through a span between the m-th node and the n-th node, based on the first index and the second index.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 18, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Shoichiro Oda, Masatake Miyabe, Setsuo Yoshida, Yasuhiko Aoki, Toru Katagiri, Goji Nakagawa, Shigeru Ishii, Yutaka Takita
  • Publication number: 20180275921
    Abstract: A storage device includes a command storage area in which a command is written, a command issuance notification area in which a notification that a command has been issued is written, a nonvolatile storage device configured to store data, and a controller configured to control an access to the nonvolatile storage device in response to the command from a host. Upon detecting that a first command is written in the command storage area, the controller executes a first step required for execution of the first command before a notification that the first command has been issued is written in the command issuance notification area.
    Type: Application
    Filed: January 31, 2018
    Publication date: September 27, 2018
    Inventors: Toru KATAGIRI, Takuya HAGA
  • Publication number: 20180145747
    Abstract: An optical transmission characteristic measurement method includes starting transmission of an optical signal from a transmitting node to a receiving node; receiving a bit error rate value measured by the receiving node and relates to the optical signal; determining whether the bit error rate value is higher than a given threshold; adjusting input power of the optical signal to lower until it is determined that the bit error rate value is higher than the given threshold when it is determined that the bit error rate value is not higher than the given threshold; estimating an optical signal to noise ratio from the bit error rate value when it is determined that the bit error rate value is higher than the given threshold; and calculating an optical signal to noise ratio based on the estimated optical signal to noise ratio and an amount of lowering of the input power.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 24, 2018
    Applicant: FUJITSU LIMITED
    Inventors: Shoichiro Oda, Toru Katagiri, Satoru Okano, Masatake Miyabe, Yasuhiko Aoki
  • Publication number: 20180139056
    Abstract: An apparatus serves as a node device included in a distributed data sharing network, and shares, by using a blockchain, a piece of event information related to an event generated in a terminal, among node devices included in the distributed data sharing network, where the blockchain is a continuously growing list of blocks which are linked and secured using cryptography. The apparatus generates a piece of event data including the piece of event information related to the event, and causes the generated piece of event data to be stored in one of the node devices included in the distributed data sharing network.
    Type: Application
    Filed: October 27, 2017
    Publication date: May 17, 2018
    Applicant: Fujitsu Limited
    Inventors: Satoshi Imai, Toru Katagiri, Motoyoshi Sekiya
  • Patent number: RE47127
    Abstract: A frame generating apparatus accommodating a client signal in an optical data transfer unit frame with a higher bit rate than the client signal includes a deserializer, a plurality of generic mapping procedure circuits, and a serializer. The deserializer deserializes the client signal into parallel signals, the number of parallel signals corresponding to the number of tributary slots used in the optical data transfer unit frame. The plurality of generic mapping procedure circuits inserts data and stuff into a frame accommodating portion of the optical data transfer unit frame based on a difference in the bit rate between the client signal and the optical data transfer unit frame. The serializer serializes the parallel signals output from the plurality of generic mapping procedure circuits.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: November 13, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Toru Katagiri, Masahiro Shioda
  • Patent number: RE48932
    Abstract: A frame generating apparatus accommodating a client signal in an optical data transfer unit frame with a higher bit rate than the client signal includes a deserializer, a plurality of generic mapping procedure circuits, and a serializer. The deserializer deserializes the client signal into parallel signals, the number of parallel signals corresponding to the number of tributary slots used in the optical data transfer unit frame. The plurality of generic mapping procedure circuits inserts data and stuff into a frame accommodating portion of the optical data transfer unit frame based on a difference in the bit rate between the client signal and the optical data transfer unit frame. The serializer serializes the parallel signals output from the plurality of generic mapping procedure circuits.
    Type: Grant
    Filed: January 17, 2018
    Date of Patent: February 15, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Toru Katagiri, Masahiro Shioda