Patents by Inventor Toru Koga

Toru Koga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6201378
    Abstract: A semiconductor integrated circuit producing a given output voltage includes first and second operational amplifiers, and first and second transistors. The first and second operational amplifiers detect a voltage difference between a voltage applied to an input terminal and at least one reference voltage. The first and second transistors are turned ON or turned OFF according to the levels of voltages output from the first and second operational amplifiers. The first operational amplifier receives the output voltage at the input terminal. When the level of the output voltage becomes lower than the reference voltage, the first operational amplifier allows the first transistor to operate so as to raise the output voltage. In contrast, the second operational amplifier receives the output voltage at the input terminal. When the level of the output voltage exceeds the reference voltage, the second operational amplifier allows the second transistor to operate so as to lower the output voltage.
    Type: Grant
    Filed: April 28, 1999
    Date of Patent: March 13, 2001
    Assignee: Fujitsu Limited
    Inventors: Satoshi Eto, Masato Matsumiya, Masato Takita, Toshikazu Nakamura, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Masatomo Hasegawa, Toru Koga, Yuki Ishii
  • Patent number: 6172537
    Abstract: A semiconductor device has a DLL circuit or the like for adjusting the phase of an external clock and producing an internal clock that lags behind by a given phase. The semiconductor device further includes a clock frequency judging unit for judging the frequency of a first clock on the basis of an indication signal indicating a delay value of the first clock in the DLL circuit or the like to output a control signal; and a clock selecting unit for selecting either one of the first clock and the second clock, in response to the control signal.
    Type: Grant
    Filed: April 6, 1999
    Date of Patent: January 9, 2001
    Assignee: Fujitsu Limited
    Inventors: Hideki Kanou, Masato Matsumiya, Satoshi Eto, Masato Takita, Ayako Kitamoto, Toshikazu Nakamura, Kuninori Kawabata, Masatomo Hasegawa, Toru Koga, Yuki Ishii
  • Patent number: 6147919
    Abstract: A semiconductor memory has memory cells arranged in arrays, direct-type sense amplifiers arranged in each column of the memory cells, for writing and reading data to and from a memory cell to be accessed, column selection lines for selecting sense amplifiers that are in a column that involves the memory cell to be accessed, write-only column selection lines for selecting sense amplifiers that are in a row that involves the memory cell to be accessed if the memory cell is accessed to write data thereto, and local drivers. The sense amplifiers are grouped, in each row, into sense amplifier blocks. The write-only column selection lines consist of first selection lines for selecting sense amplifier blocks that are in the row that involves the memory cell to be accessed for data write and second selection lines for selecting sense amplifiers that are contained in the selected sense amplifier blocks.
    Type: Grant
    Filed: March 23, 1999
    Date of Patent: November 14, 2000
    Assignee: Fujitsu Limited
    Inventors: Kuninori Kawabata, Masato Matsumiya, Satoshi Eto, Masato Takita, Toshikazu Nakamura, Masatomo Hasegawa, Hideki Kanou, Ayako Kitamoto, Toru Koga, Yuki Ishii, Akira Kikutake, Yuichi Uzawa
  • Patent number: 6141274
    Abstract: In a semiconductor integrated circuit having the function of executing a pre-charge operation of a data bus when data is transferred to the data bus from a plurality of driver circuits connected to the data bus, a reset circuit for executing the pre-charge operation of the data bus is constituted so as to start the pre-charge operation of the data bus upon receiving an end timing of a strobe signal. Preferably, the reset circuit detects that the data bus reaches a pre-charge level for executing the pre-charge operation, and then terminates the pre-charge operation. On the other hand, in a semiconductor integrated circuit having a data latch function by a pipeline system when the data is read out from a memory cell, etc.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: October 31, 2000
    Assignee: Fujitsu Limited
    Inventors: Satoshi Eto, Masato Matsumiya, Yuichi Uzawa, Kuninori Kawabata, Akira Kikutake, Toru Koga
  • Patent number: 6130849
    Abstract: In a data bus amplifier activation method for a semiconductor memory device having a memory cell array, a column selection circuit for selecting a column in the memory cell array, a read data bus for transferring read data, output from the column selected by the column selection circuit, to a read data bus amplifier, and a write data bus for transferring write data, output from a write data bus amplifier, to the column selected by the column selection circuit, the read data bus amplifier or the write data bus amplifier is activated by detecting the selection of the column effected by the column selection circuit.
    Type: Grant
    Filed: April 27, 1999
    Date of Patent: October 10, 2000
    Assignee: Fujitsu Limited
    Inventors: Kuninori Kawabata, Masato Matsumiya, Satoshi Eto, Yuichi Uzawa, Toru Koga, Akira Kikutake
  • Patent number: 6115284
    Abstract: The present invention relates to a memory device including memory cells each formed of a cell transistor connected to bit and word line and a cell capacitor. The memory device includes a pre-charging circuit for pre-charging bit line to a first voltage, a sense amplifier for detecting voltages of bit lines and driving the bit lines to a second voltage for H level or a third voltage for L level, and a word line driving circuit for driving word lines to make the writing voltage for H level of the cell capacitor to a fourth voltage lower than the second voltage. The present invention is characterized in that the first voltage is lower than an intermediate value between the second and third voltages. According to the present invention, it becomes possible to prevent the voltage V.sub.
    Type: Grant
    Filed: May 25, 1999
    Date of Patent: September 5, 2000
    Assignee: Fujitsu Limited
    Inventors: Masato Matsumiya, Satoshi Eto, Masato Takita, Toshikazu Nakamura, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Masatomo Hasegawa, Toru Koga, Yuki Ishii
  • Patent number: 6111802
    Abstract: A semiconductor memory device includes a memory cell connected to a bit line and a word line, a bit line precharge circuit which precharges the bit line to a ground voltage, and a word decoder which sets the word line to a negative voltage when the word line is not selected.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: August 29, 2000
    Assignee: Fujitsu Limited
    Inventors: Hideki Kano, Masato Matsumiya, Masato Takita, Toru Koga, Satoshi Eto, Toshikazu Nakamura, Mitsuhiro Higashiho, Kuninori Kawabata, Ayako Kitamoto
  • Patent number: 6072749
    Abstract: This invention is a memory device with a structure that has eliminated the logic circuit using I/O mask signal DQM from within the critical path from the clock CLK to the predecoder and column decoder for generating column selection signal CL. The logic circuit using I/O mask signal DQM within the critical path for generating column selection signals is eliminated, and the time from when the clock is supplied until the column selection signal is generated is made as short as possible. On the other hand, to make an I/O mask possible during burst write mode, drive control of the write amplifier is performed based on I/O mask signal DQM. Specifically, activation of the write amplifier is prohibited or allowed in response to the I/O mask signal DQM.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: June 6, 2000
    Assignee: Fujitsu Limited
    Inventors: Toshikazu Nakamura, Masato Matsumiya, Satoshi Eto, Masato Takita, Ayako Kitamoto, Kuninori Kawabata, Hideki Kanou, Masatomo Hasegawa, Toru Koga, Yuki Ishii
  • Patent number: 6049239
    Abstract: A variable delay circuit includes a first gate having a first delay amount, and a second gate having a second delay amount greater than the first delay amount. A difference between the first delay amount and the second delay time is less than the first delay amount.
    Type: Grant
    Filed: September 22, 1997
    Date of Patent: April 11, 2000
    Assignee: Fujitsu Limited
    Inventors: Satoshi Eto, Masao Taguchi, Masato Matsumiya, Toshikazu Nakamura, Masato Takita, Mitsuhiro Higashiho, Toru Koga, Hideki Kano, Ayako Kitamoto, Kuninori Kawabata, Koichi Nishimura, Yoshinori Okajima
  • Patent number: 5943253
    Abstract: A semiconductor memory device includes at least one cell block including an array of memory cells, a plurality of sense amplifiers which temporarily hold data of the memory cells, a first data bus connected to the plurality of sense amplifiers via first gates, and a second data bus having a direct electrical connection to the first data bus and being laid out to extend through a position of the at least one cell block.
    Type: Grant
    Filed: April 9, 1998
    Date of Patent: August 24, 1999
    Assignee: Fujitsu Limited
    Inventors: Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Masato Takita, Mitsuhiro Higashiho, Toru Koga, Hideki Kano, Ayako Kitamoto, Kuninori Kawabata
  • Patent number: 5936912
    Abstract: An electronic device includes a first circuit which refers to an external clock and thus produces a first internal clock, and a second circuit which refers to the first internal clock and thus produces a second internal clock. The first circuit has a first phase error between the external clock and the first internal clock, and the second circuit has a second phase error between the first internal clock and the second internal clock. The first phase error has a sign reverse to that of the second phase error.
    Type: Grant
    Filed: March 4, 1998
    Date of Patent: August 10, 1999
    Assignee: Fujitsu Limited
    Inventors: Kuninori Kawabata, Masato Matsumiya, Satoshi Eto, Toshikazu Nakamura, Mitsuhiro Higashiho, Masato Takita, Toru Koga, Hideki Kanou, Ayako Kitamoto
  • Patent number: 5905390
    Abstract: An inductive load drive circuit includes a transistor for pulling-in an excitation current having a predetermined polarity and generated by an inductive load. The transistor is turned-on by a first idling loop when a drive voltage of the inductive load has a negative polarity, and the transistor is turned-on by a second idling loop when the drive voltage has a positive polarity. Though both of the first idling loop and the second idling operate on the basis of the drive voltage, in pulling the excitation current into the circuit, the drive voltage reaches a lower limit of a dynamic range at a time that the first idling loop is suitably operated while the drive voltage reaches an upper limit of the dynamic range at a time that the second idling loop is suitably operated.
    Type: Grant
    Filed: September 24, 1997
    Date of Patent: May 18, 1999
    Assignee: Rohm, Co., Ltd.
    Inventor: Toru Koga
  • Patent number: 5357464
    Abstract: Disclosed is a semiconductor memory having a self-amplifying cell structure, using (1) a writing transistor and (2) a reading transistor with a floating gate as a charge storage node for each memory cell, and a method of fabricating the memory cell. The writing transistor and reading transistor are of opposite conductivity type to each other; for example, the writing transistor uses a P-channel MOS transistor and the reading transistor (having the floating gate) uses an N-channel MOS transistor. The floating gate of the reading transistor is connected to a single bit line through a source-drain path of the writing transistor, the source-drain path of the reading transistor is connected between the single bit line and a predetermined potential, and the gate electrodes of the writing and reading transistors are connected to a single word line. At least the reading transistor can be formed in a trench, and the word line can be formed overlying the writing transistor and the reading transistor in the trench.
    Type: Grant
    Filed: February 26, 1993
    Date of Patent: October 18, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Shuji Shukuri, Toru Koga, Shinichiro Kimura, Digh Hisamoto, Kazuhiko Sagara, Tokuo Kure, Eiji Takeda