Patents by Inventor Toru Maniwa

Toru Maniwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190273541
    Abstract: A multiantenna communication device forms a directional beam by adding an antenna weight to respective signals of a plurality of antenna elements. The multiantenna communication device includes: a processor that executes performing distortion compensation on a transmission signal by using a distortion compensation coefficient; a plurality of power amplifiers that are provided corresponding to the antenna elements, and that amplify the transmission signal subjected to the distortion compensation by the processor; a multiplexer that multiplexes signals output from the power amplifiers to feed back; and an analog/digital (A/D) converter that A/D converts a multiplex feedback signal that is obtained by the multiplexer, wherein the processor executes updating the distortion compensation coefficient by using the multiplex feedback signal A/D converted by the A/D converter and the transmission signal.
    Type: Application
    Filed: February 27, 2019
    Publication date: September 5, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Takenori Ohshima, Yoji Ohashi, Hiroyoshi Ishikawa, Atsushi Honda, Toru Maniwa, Alexander Nikolaevich Lozhkin, Toshio Kawasaki, Yuichi Utsunomiya, Tomoya Ota
  • Publication number: 20180062696
    Abstract: A passive intermodulation (PIM) canceller of a communication device includes a combining unit, a replica generating unit, and a delay measuring instrument. The replica generating unit generates an intermodulation signal based on the amount of delay of each transmission signal. The combining unit cancels out the intermodulation signal from the reception signal using the generated intermodulation signal. The delay measuring instrument delays a transmission signal x2 included in a plurality of transmission signals by different first amounts of delay. The delay measuring instrument generates an intermediate signal Sm1 by multiplying the delayed transmission signal x2 to the reception signal. The delay measuring instrument calculates, based on the correlation values of the intermediate signal Sm1 corresponding to each first amount of delay and a transmission signal x1 included in the plurality of transmission signals, the amount of delay of the transmission signal x1 with respect to the intermodulation signal.
    Type: Application
    Filed: July 12, 2017
    Publication date: March 1, 2018
    Applicant: FUJITSU LIMITED
    Inventors: TOSHIO KAWASAKI, Nobuhisa Aoki, TORU MANIWA, Tadahiro Sato, Yusuke Tobisu, Hiroshi Towata
  • Publication number: 20170208598
    Abstract: A distortion cancel device includes: a first acquiring unit that acquires a plurality of transmission signals including at least two transmission signals that are wirelessly transmitted at an identical frequency; a second acquiring unit that acquires a reception signal to which an intermodulation signal generated due to the transmission signals is attached; and a processor that executes a process including: determining a ratio of the transmission signals acquired by the first acquiring unit and wirelessly transmitted at the identical frequency; generating a ratio signal for each frequency from the transmission signals in accordance with the determined ratio; generating a cancel signal corresponding to the intermodulation signal by using an arithmetic expression that uses the generated ratio signal; and combining the generated cancel signal with the reception signal acquired by the second acquiring unit.
    Type: Application
    Filed: January 9, 2017
    Publication date: July 20, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Nobuhisa Aoki, TOSHIO KAWASAKI, TORU MANIWA, Tadahiro Sato, Yusuke Tobisu, Hiroshi Towata
  • Publication number: 20170207862
    Abstract: A distortion cancellation device includes a first acquiring unit that acquires a plurality of transmission signals that are wirelessly transmitted at different frequencies; a second acquiring unit that acquires a reception signal to which an intermodulation signal generated due to the plurality of the transmission signals is added; and a processor that executes a process including acquiring a gain difference between the plurality of the transmission signals generated when the plurality of the transmission signals acquired by the first acquiring unit is sent to a generation source of the intermodulation signal, generating, by an arithmetic expression using both the acquired gain difference and the plurality of the transmission signals, a cancellation signal associated with the intermodulation signal, and combining the generated cancellation signal with the reception signal acquired by the second acquiring unit.
    Type: Application
    Filed: January 9, 2017
    Publication date: July 20, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Nobuhisa Aoki, TOSHIO KAWASAKI, TORU MANIWA, Tadahiro Sato, Yusuke Tobisu, Hiroshi Towata
  • Publication number: 20170207886
    Abstract: A delay measuring instrument includes a generating unit and a calculating unit. The generating unit is, for example, a multiplier. The calculating unit is, for example, a maximum value detecting unit. The generating unit generates an intermediate signal by multiplying one of transmission signals or the complex conjugate of the one of the transmission signals included in the plurality of transmission signals that are transmitted at different frequencies by a reception signal that includes therein an intermodulation signal generated by the plurality of the transmission signals. The calculating unit calculates, based on a correlation value between the intermediate signal and the other one of the transmission signals included in the plurality of the transmission signals, an amount of delay of the other one of the transmission signals with respect to the intermodulation signal.
    Type: Application
    Filed: December 13, 2016
    Publication date: July 20, 2017
    Inventors: TOSHIO KAWASAKI, Nobuhisa Aoki, TORU MANIWA, Tadahiro Sato, Yusuke Tobisu, Hiroshi Towata
  • Publication number: 20160380668
    Abstract: A communication device includes a sending unit that sends a plurality of signals that are to be wirelessly sent with different frequencies; an acquiring unit that acquires a reception signal to which an intermodulation signal that is produced due to intermodulation of the plurality of signals is added; and a processor that is connected to the sending unit and the acquiring unit. The processor generates, on the basis of the plurality of signals sent by the sending unit, a cancellation signal corresponding to the intermodulation signal and combines the generated cancellation signal with the reception signal acquired by the acquiring unit.
    Type: Application
    Filed: June 9, 2016
    Publication date: December 29, 2016
    Inventors: Nobuhisa AOKI, Toshio KAWASAKI, Toru MANIWA, Tadahiro SATO, Yusuke TOBISU, Akifumi ADACHI, Eizou ISHIZU
  • Patent number: 9319012
    Abstract: An amplifying apparatus, including an amplitude-phase conversion unit to separate an input signal into first and second signals, wherein a phase difference between the first and second signals depends on an amplitude of the input signal, a first amplifying unit, a first matching circuit including a main line and a first harmonic processing circuit, wherein a length of the line of the first harmonic processing circuit short-circuits a harmonic, a second amplifying unit, a second matching circuit including a main line and a second harmonic processing circuit, wherein a length of the line of the second harmonic processing circuit short-circuits a harmonic, and an output synthesis unit to synthesize outputs from the first and second matching circuits, wherein a distance from the first amplifying unit to the first harmonic processing circuit differs from a distance from the second amplifying unit to the second harmonic processing circuit.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: April 19, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Toru Maniwa, Shigekazu Kimura, Nobuhisa Aoki
  • Patent number: 9270235
    Abstract: An amplifier includes: an amplifying device configured to amplify an input signal; and a matching circuit coupled to the amplifying device, and including an impedance transformer and a parallel resonance circuit coupled to a wiring which spans from the impedance transformer to the amplifying device, wherein a circuit length of the impedance transformer is longer than one-fourth of wavelength of an electronic wave having a frequency which is substantially equal to a resonance frequency of the parallel resonance circuit.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: February 23, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Nobuhisa Aoki, Toru Maniwa
  • Patent number: 9059664
    Abstract: An amplifier includes a signal processing circuit configured to generate an orthogonal signal orthogonal to an input signal; a first D/A converter configured to convert the orthogonal signal into a first analog signal; a second D/A converter configured to convert the input signal into a second analog signal; and an analog computing circuit configured to generate a constant envelope signal based on the first analog signal from the first D/A converter and the second analog signal from the second D/A converter.
    Type: Grant
    Filed: October 30, 2012
    Date of Patent: June 16, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Toru Maniwa, Shigekazu Kimura
  • Publication number: 20150102859
    Abstract: An amplifying apparatus includes a decomposer, two amplifiers, a combiner, and a controller. The decomposer decomposes an input signal into two signals having different phases. The two amplifiers amplify the decomposed two signals, respectively. The combiner combines output of the amplifiers. The controller controls at least one of waveform information of at least one of the two signals and an operating state of the two amplifiers such that an output characteristic of the combiner matches a desired characteristic.
    Type: Application
    Filed: September 10, 2014
    Publication date: April 16, 2015
    Inventors: TORU MANIWA, TOSHIO KAWASAKI, TOMONORI SATO, Shigekazu Kimura, NAOJI FUJINO
  • Publication number: 20150008983
    Abstract: An amplifying apparatus, including an amplitude-phase conversion unit to separate an input signal into first and second signals, wherein a phase difference between the first and second signals depends on an amplitude of the input signal, a first amplifying unit, a first matching circuit including a main line and a first harmonic processing circuit, wherein a length of the line of the first harmonic processing circuit short-circuits a harmonic, a second amplifying unit, a second matching circuit including a main line and a second harmonic processing circuit, wherein a length of the line of the second harmonic processing circuit short-circuits a harmonic, and an output synthesis unit to synthesize outputs from the first and second matching circuits, wherein a distance from the first amplifying unit to the first harmonic processing circuit differs from a distance from the second amplifying unit to the second harmonic processing circuit.
    Type: Application
    Filed: June 30, 2014
    Publication date: January 8, 2015
    Inventors: TORU MANIWA, Shigekazu Kimura, Nobuhisa Aoki
  • Patent number: 8896372
    Abstract: A first amplification section and a second amplification section included in an amplification apparatus amplify two constant amplitude signals generated by vector decomposition. An impedance inverting circuit inverts the impedance of the signal amplified by the second amplification section. A combining circuit corrects the phases of the signal amplified by the first amplification section and the signal whose impedance is inverted by the impedance inverting circuit, and combines and outputs these signals. The combining circuit includes a line which is (?/4)+? in length and which is an asymmetrical circuit element and a line which is (?/4)?? in length and which is an asymmetrical circuit element.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: November 25, 2014
    Assignee: Fujitsu Limited
    Inventor: Toru Maniwa
  • Patent number: 8890620
    Abstract: A power amplifier includes a first matching circuit configured to perform harmonic processing of an input signal, and a second matching circuit configured to perform the harmonic processing of an output signal, the output signal being generated by amplifying a power of the input signal. The power amplifier rotates a phase of output impedance at a matching point of the harmonic included in the generated output signal when the power of the input signal is decreased from a value higher than a certain value to a value lower than the certain value.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: November 18, 2014
    Assignee: Fujitsu Limited
    Inventors: Ken Tamanoi, Toru Maniwa
  • Publication number: 20140292405
    Abstract: An amplification device includes: an amplitude adjustment circuit configured to adjust an amplitude level of an input signal so as to keep the amplitude level within a given range; an amplifier configured to amplify the adjusted signal; and a circuitry configured to change an amplitude level of the amplified signal, based on the amplitude level of the input signal and a first distortion compensation corresponding to the amplitude level of the input signal.
    Type: Application
    Filed: March 25, 2014
    Publication date: October 2, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Takeshi TAKANO, Shigekazu KIMURA, Ken TAMANOI, Masakazu KOJIMA, Toru MANIWA, Yasuyuki OISHI, Michiharu NAKAMURA, Kazuo NAGATANI
  • Publication number: 20140285262
    Abstract: A control device of a power amplifier includes: a limiter configured to limit a level of an input signal to the power amplifier; and a control unit configured to, when the limiter operates, make an operation voltage of the power amplifier invariable and control load of an output matching circuit of the power amplifier based on an amplitude of the input signal, and, when the limiter does not operate, to make the load of the output matching circuit invariable and control the operation voltage of the power amplifier.
    Type: Application
    Filed: November 26, 2013
    Publication date: September 25, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Masakazu KOJIMA, Shigekazu Kimura, Takeshi Takano, Toru Maniwa, Ken Tamanoi
  • Patent number: 8836432
    Abstract: An amplifier includes an amplifying element that amplifies an input signal; an output terminal that outputs the signal amplified by the amplifying element; a matching circuit disposed in series between the amplifying element and the output terminal, and performing impedance matching; an impedance converter disposed in series between the amplifying element and the matching circuit or between the matching circuit and the output terminal; and a first resonator and a second resonator connected at the ends of the impedance converter.
    Type: Grant
    Filed: January 13, 2013
    Date of Patent: September 16, 2014
    Assignee: Fujitsu Limited
    Inventors: Toru Maniwa, Shigekazu Kimura
  • Publication number: 20140218105
    Abstract: An amplifier includes: an amplifying device configured to amplify an input signal; and a matching circuit coupled to the amplifying device, and including an impedance transformer and a parallel resonance circuit coupled to a wiring which spans from the impedance transformer to the amplifying device, wherein a circuit length of the impedance transformer is longer than one-fourth of wavelength of an electronic wave having a frequency which is substantially equal to a resonance frequency of the parallel resonance circuit.
    Type: Application
    Filed: November 14, 2013
    Publication date: August 7, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Nobuhisa AOKI, Toru MANIWA
  • Publication number: 20140055199
    Abstract: A power amplification device, includes: an amplifier to amplify an input signal; a switched capacitor, provided at an output stage of the amplifier, to change capacitance based on a first control signal; a matching unit, provided at the output stage of the amplifier and including a varactor pair in which two varactor diodes are coupled in series or a varactor pair in which two varactor diodes are coupled in parallel, to change capacitance based on a second control signal; a detection circuit to detect power of the input signal; a quantization circuit to quantize a detected power value, form a quantized bit string having a high-order bit group and a low-order bit group, and output the high-order bit group as the first control signal to the switched capacitor; and a conversion circuit to convert the low-order bit group into an analog value and form the second control signal.
    Type: Application
    Filed: June 6, 2013
    Publication date: February 27, 2014
    Inventors: Takeshi TAKANO, Masakazu Kojima, Michiharu Nakamura, Toru Maniwa, Shigekazu Kimura, Ken Tamanoi
  • Patent number: 8629809
    Abstract: A tag patch antenna includes: a slit formed in the vicinity of an edge of an antenna pattern along a part of the edge; and a feeding point to which a tag LSI is connected and which is formed by cutting an intermediate portion of the part of the edge separated by the slit from a body of the antenna pattern by a width of the slit.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: January 14, 2014
    Assignees: Fujitsu Limited, Fujitsu Frontech Limited
    Inventors: Takashi Yamagajo, Toru Maniwa, Manabu Kai, Yoshiyasu Sugimura, Shunji Baba
  • Patent number: 8618995
    Abstract: A metal pipe includes a slot having a predetermined length in a longitudinal direction of the metal pipe and a wireless tag that is placed inside the metal pipe and includes a power feeding unit to feed electric power to the slot and an IC chip connected to the power feeding unit, thereby functioning as an antenna of the wireless tag. The metal pipe is thus managed by the wireless tag.
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: December 31, 2013
    Assignee: Fujitsu Limited
    Inventors: Takashi Yamagajo, Toru Maniwa, Manabu Kai