Patents by Inventor Toru Takeshita

Toru Takeshita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11005445
    Abstract: An electronic component including a pad electrode provided on a wiring electrode and a Au bump provided on the pad electrode, wherein the uppermost layer of the wiring electrode is a first Ti layer, the uppermost layer of the pad electrode is a Au layer, and the thickness of the first Ti layer in at least a portion on which the Au bump is superposed in plan view is greater than the thickness of at least a portion of the first Ti layer in a portion on which the Au bump is not superposed in plan view.
    Type: Grant
    Filed: December 12, 2019
    Date of Patent: May 11, 2021
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Ryuta Yamada, Yasuyuki Toyota, Masaharu Fujiya, Toru Takeshita, Masaaki Shimada
  • Patent number: 10812042
    Abstract: In an electronic component, electrodes defining functional portions are provided on a piezoelectric substrate. In order to define a hollow portion which the functional portions face, there are provided a first support with a frame shape, and second supports on the piezoelectric substrate in an inner side region surrounded by the first support. A cover is laminated on the first support as well as on the second supports to define the hollow portion. A height of each of the second supports is higher than a height of the first support.
    Type: Grant
    Filed: August 10, 2017
    Date of Patent: October 20, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Toru Takeshita
  • Patent number: 10756698
    Abstract: An elastic wave device includes a multilayer film including a piezoelectric thin film laminated on a support substrate. In a region outside a region in which an IDT electrode is provided, the multilayer film is not disposed. A first insulating layer extends from at least a portion of the region to a region on the piezoelectric thin film. A wiring electrode extends to a region on the first insulating layer from a region on the piezoelectric thin film and to extend to a region on a portion of the first insulating layer located in the region. A support layer including a cavity defining a hollow space is provided on the support substrate. The support layer includes, on the wiring electrode, a portion extending from the region to a region above an inner end of the first insulating layer.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: August 25, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takashi Yamane, Tsutomu Takai, Toru Takeshita
  • Publication number: 20200228090
    Abstract: An acoustic wave device includes an acoustic wave substrate including a first main surface and a second main surface, IDT electrodes provided on the first main surface, and sealing resin covering at least the second main surface of the acoustic wave substrate. A hollow is provided in a region where the IDT electrodes on the first main surface of the acoustic wave substrate is located. The sealing resin has through-holes each extending from a top surface 13B of the sealing resin to the second main surface of the acoustic wave substrate. The acoustic wave substrate is made of silicon or includes a layer made of silicon.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 16, 2020
    Inventor: Toru TAKESHITA
  • Patent number: 10715102
    Abstract: A filter device includes a first filter chip including a first signal terminal and a second filter chip including a second signal terminal that are mounted above a package substrate including a substrate main body. First and second signal electrode pads are provided on a first main surface of the package substrate and are respectively joined to the first and second signal terminals. First and second outer terminals are provided on a second main surface of the substrate main body. The first and second signal electrode pads and the first and second outer terminals are connected to each other with first and second wirings, respectively. The second outer terminal is located at the first signal electrode pad side and the first outer terminal is located at the second signal electrode pad side when seen from above.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 14, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Toru Takeshita
  • Publication number: 20200204152
    Abstract: An electronic component including a pad electrode provided on a wiring electrode and a Au bump provided on the pad electrode, wherein the uppermost layer of the wiring electrode is a first Ti layer, the uppermost layer of the pad electrode is a Au layer, and the thickness of the first Ti layer in at least a portion on which the Au bump is superposed in plan view is greater than the thickness of at least a portion of the first Ti layer in a portion on which the Au bump is not superposed in plan view.
    Type: Application
    Filed: December 12, 2019
    Publication date: June 25, 2020
    Inventors: Ryuta YAMADA, Yasuyuki TOYOTA, Masaharu FUJIYA, Toru TAKESHITA, Masaaki SHIMADA
  • Patent number: 10622965
    Abstract: A surface acoustic wave device assembly includes a collective board, first circuit portions provided on the collective board and respectively including first hot terminals and first ground terminals, a second circuit portion provided on the collective board and including second hot terminals and second ground terminals, and a power supply wiring provided on the collective board so as to surround the periphery of the first circuit portions and the second circuit portion. The first circuit portions include surface acoustic wave devices defining band pass filters. The second circuit portion defines a band pass filter. The first ground terminals and first hot terminals, and the second ground terminal are connected to the power supply wiring, the second hot terminals are not connected to the power supply wiring, and pass bands of the surface acoustic wave devices and a pass band of the band pass filter defined by the second circuit portion are the same or substantially the same.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: April 14, 2020
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Toru Takeshita, Seiji Kai, Takashi Naka, Motoji Tsuda, Mitsuyoshi Hira
  • Publication number: 20190305748
    Abstract: An elastic wave device includes a multilayer film including a piezoelectric thin film laminated on a support substrate. In a region outside a region in which an IDT electrode is provided, the multilayer film is not disposed. A first insulating layer extends from at least a portion of the region to a region on the piezoelectric thin film. A wiring electrode extends to a region on the first insulating layer from a region on the piezoelectric thin film and to extend to a region on a portion of the first insulating layer located in the region. A support layer including a cavity defining a hollow space is provided on the support substrate. The support layer includes, on the wiring electrode, a portion extending from the region to a region above an inner end of the first insulating layer.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 3, 2019
    Inventors: Takashi YAMANE, Tsutomu TAKAI, Toru TAKESHITA
  • Publication number: 20190288666
    Abstract: An acoustic wave device includes an element substrate having piezoelectricity, an interdigital transducer electrode provided on the element substrate, and a mold resin covering the element substrate. When viewed in a cross section, the element substrate includes an interdigital transducer formation region in which the interdigital transducer electrode is provided and a pair of interdigital transducer non-formation regions in which the interdigital transducer electrode is not provided and located on both sides of the interdigital transducer formation region, and a thickness dimension of a center portion, in a width direction, of the interdigital transducer formation region is less than at least one of thickness dimensions of center portions, in the width direction, of the interdigital transducer non-formation regions.
    Type: Application
    Filed: June 6, 2019
    Publication date: September 19, 2019
    Inventor: Toru TAKESHITA
  • Publication number: 20180287588
    Abstract: A filter device includes a first filter chip including a first signal terminal and a second filter chip including a second signal terminal that are mounted above a package substrate including a substrate main body. First and second signal electrode pads are provided on a first main surface of the package substrate and are respectively joined to the first and second signal terminals. First and second outer terminals are provided on a second main surface 3b of the substrate main body. The first and second signal electrode pads and the first and second outer terminals are connected to each other with first and second wirings, respectively. The second outer terminal is located at the first signal electrode pad side and the first outer terminal is located at the second signal electrode pad side when seen from above.
    Type: Application
    Filed: June 7, 2018
    Publication date: October 4, 2018
    Inventor: Toru TAKESHITA
  • Publication number: 20170338797
    Abstract: In an electronic component, electrodes defining functional portions are provided on a piezoelectric substrate. In order to define a hollow portion which the functional portions face, there are provided a first support with a frame shape, and second supports on the piezoelectric substrate in an inner side region surrounded by the first support. A cover is laminated on the first support as well as on the second supports to define the hollow portion. A height of each of the second supports is higher than a height of the first support.
    Type: Application
    Filed: August 10, 2017
    Publication date: November 23, 2017
    Inventor: Toru TAKESHITA
  • Publication number: 20170317659
    Abstract: A surface acoustic wave device assembly includes a collective board, first circuit portions provided on the collective board and respectively including first hot terminals and first ground terminals, a second circuit portion provided on the collective board and including second hot terminals and second ground terminals, and a power supply wiring provided on the collective board so as to surround the periphery of the first circuit portions and the second circuit portion. The first circuit portions include surface acoustic wave devices defining band pass filters. The second circuit portion defines a band pass filter. The first ground terminals and first hot terminals, and the second ground terminal are connected to the power supply wiring, the second hot terminals are not connected to the power supply wiring, and pass bands of the surface acoustic wave devices and a pass band of the band pass filter defined by the second circuit portion are the same or substantially the same.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Toru TAKESHITA, Seiji KAI, Takashi NAKA, Motoji TSUDA, Mitsuyoshi HIRA
  • Patent number: 7560236
    Abstract: The present invention provides a method which can enhance the precision of identification of bacterial species using a T-RFLP method and achieve, by itself, the identification of bacteria constituting a bacterial flora and the tracing of distribution changes thereof. The present invention provides a method for analyzing a bacterial community including: amplifying DNAs extracted from a bacterial community by PCR using 16S rRNA genes as templates and fluorescently labeled primers; cleaving the amplification products with a restriction enzyme to thereby obtain sample PCR fragments; electrophoresing the sample PCR fragments together with size standard PCR fragments; and comparing the mobilities thereof to thereby determine the sizes of the sample PCR fragments, wherein PCR fragments amplified by using, as a template, a 16S rRNA gene derived from a bacterium contained in the bacterial community to be analyzed are used as the size standards.
    Type: Grant
    Filed: June 7, 2007
    Date of Patent: July 14, 2009
    Assignee: Kao Corporation
    Inventors: Yoshihisa Yamashita, Yoshio Nakano, Toru Takeshita
  • Publication number: 20080305475
    Abstract: The present invention provides a method which can enhance the precision of identification of bacterial species using a T-RFLP method and achieve, by itself, the identification of bacteria constituting a bacterial flora and the tracing of distribution changes thereof. The present invention provides a method for analyzing a bacterial community including: amplifying DNAs extracted from a bacterial community by PCR using 16S rRNA genes as templates and fluorescently labeled primers; cleaving the amplification products with a restriction enzyme to thereby obtain sample PCR fragments; electrophoresing the sample PCR fragments together with size standard PCR fragments; and comparing the mobilities thereof to thereby determine the sizes of the sample PCR fragments, wherein PCR fragments amplified by using, as a template, a 16S rRNA gene derived from a bacterium contained in the bacterial community to be analyzed are used as the size standards.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 11, 2008
    Applicant: Kao Corporation
    Inventors: Yoshihisa YAMASHITA, Yoshio Nakano, Toru Takeshita
  • Patent number: 7184512
    Abstract: A clock generator is configured to generate, on the basis of an oscillation frequency clock of a voltage-controlled oscillator, a first signal having a phase the same as the oscillation frequency clock, a second signal having a phase delayed by a first phase amount to the first signal and a third signal having a phase delayed by a second phase amount to the first signal. A phase detection circuit is configured to provide a phase control on the basis of a phase difference between the third signal and an input signal. A frequency detection circuit is configured to sample the first and second signals synchronously with the input signal, thereby performing a frequency control for the voltage-controlled oscillator on the basis of the sampled signals.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: February 27, 2007
    Assignee: Sony Corporation
    Inventors: Toru Takeshita, Takashi Nishimura
  • Patent number: 6915081
    Abstract: The invention provides a PLL circuit wherein, even if the duty ratio of an input signal varies, stabilized PLL operation is achieved. The PLL circuit includes a phase detection circuit and a frequency detection circuit. The frequency detection circuit includes a pair of D-type flip-flops for sampling first and second clock signals having different phases from each other in synchronism with an input signal at each rising or falling changing point of the input signal for each period, and a control logic circuit for logically operating the signals sampled by the D-type flip-flops and the signals sampled successively subsequently by the D-type flip-flops. The control logic circuit generates an UP pulse signal or a DOWN pulse signal based on a result of the arithmetic operation.
    Type: Grant
    Filed: October 17, 2001
    Date of Patent: July 5, 2005
    Assignee: Sony Corporation
    Inventors: Toru Takeshita, Takashi Nishimura
  • Publication number: 20030142775
    Abstract: A clock generator is configured to generate, on the basis of an oscillation frequency clock of a voltage-controlled oscillator, a first signal having a phase the same as the oscillation frequency clock, a second signal having a phase delayed by a first phase amount to the first signal and a third signal having a phase delayed by a second phase amount to the first signal. A phase detection circuit is configured to provide a phase control on the basis of a phase difference between the third signal and an input signal. A frequency detection circuit is configured to sample the first and second signals in synchronism with the input signal, thereby performing a frequency control for the voltage-controlled oscillator on the basis of the sampled signals.
    Type: Application
    Filed: January 28, 2003
    Publication date: July 31, 2003
    Inventors: Toru Takeshita, Takashi Nishimura
  • Patent number: 6545546
    Abstract: The invention provides a PLL circuit wherein, even if the duty ratio of an input signal varies, the convergence time required for frequency detection of a frequency detection circuit is short and wrong operation of the frequency detection circuit with a control signal is less likely to occur. A clock generator produces, based on an oscillation frequency clock of a VCO, a first clock signal of the same phase, a second clock signal having a phase delayed by 90 degrees from that of the first clock signal, and a third clock signal having a phase delayed by 45 degrees from that of the first clock signal. A phase detection circuit performs phase control based on the phase difference between the third clock signal and an input signal, and a frequency detection circuit fetches the first and second clock signals in synchronism with the input signal and performs frequency control based on the fetched signals.
    Type: Grant
    Filed: October 18, 2001
    Date of Patent: April 8, 2003
    Assignee: Sony Corporation
    Inventors: Toru Takeshita, Takashi Nishimura
  • Publication number: 20020057479
    Abstract: The invention provides a PLL circuit wherein, even if the duty ratio of an input signal varies, stabilized PLL operation is achieved. The PLL circuit includes a phase detection circuit and a frequency detection circuit. The frequency detection circuit includes a pair of D-type flip-flops for sampling first and second clock signals having different phases from each other in synchronism with an input signal at each rising or falling changing point of the input signal for each period, and a control logic circuit for logically operating the signals sampled by the D-type flip-flops and the signals sampled successively subsequently by the D-type flip-flops. The control logic circuit generates an UP pulse signal or a DOWN pulse signal based on a result of the arithmetic operation.
    Type: Application
    Filed: October 17, 2001
    Publication date: May 16, 2002
    Inventors: Toru Takeshita, Takashi Nishimura
  • Publication number: 20020053950
    Abstract: The invention provides a PLL circuit wherein, even if the duty ratio of an input signal varies, the convergence time required for frequency detection of a frequency detection circuit is short and wrong operation of the frequency detection circuit with a control signal is less likely to occur. A clock generator produces, based on an oscillation frequency clock of a VCO, a first clock signal of the same phase, a second clock signal having a phase delayed by 90 degrees from that of the first clock signal, and a third clock signal having a phase delayed by 45 degrees from that of the first clock signal. A phase detection circuit performs phase control based on the phase difference between the third clock signal and an input signal, and a frequency detection circuit fetches the first and second clock signals in synchronism with the input signal and performs frequency control based on the fetched signals.
    Type: Application
    Filed: October 18, 2001
    Publication date: May 9, 2002
    Inventors: Toru Takeshita, Takashi Nishimura