Patents by Inventor Toru Yamauchi

Toru Yamauchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210039571
    Abstract: A wire harness protector includes a protector body and a cover. The protector body is configured to accommodate a corrugated tube extending in a front-rear direction and through which a wire harness is inserted. The cover is configured to cover an opening of the protector body. A first front end being one of a front end of the protector body or a front end of the cover is arranged rearward of a second front end being the other of the front ends. A portion of the wire harness protector located at the first front end includes a first rib configured to hold the corrugated tube. A portion of wire harness the protector facing the first front end and located rearward of the second front end includes a second rib configured to hold the corrugated tube.
    Type: Application
    Filed: August 6, 2020
    Publication date: February 11, 2021
    Applicant: Yazaki Corporation
    Inventors: Akinori YAMAUCHI, Toru KATO
  • Patent number: 10885984
    Abstract: A memory device comprising a semiconductor substrate in which a memory cell region and a peripheral circuitry region are defined, wherein the memory cell region has a plurality of non-volatile memory cells arranged in one or more arrays and the peripheral circuitry region has at least one sense amplifier region comprised of at least one low voltage transistor. Further, a deep N-well region is formed in the substrate, wherein the memory cell region and the peripheral circuitry region are placed on the deep N-well region such that, in the event that a high erase voltage (VERA) is applied to the memory cell region during an erase operation, the high erase voltage is applied to all terminals of the at least one low voltage resistor, thereby protecting the low voltage transistor by preventing it from experiencing a large voltage difference between its terminals.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: January 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Hiroki Yabe, Koichiro Hayashi, Takuya Ariki, Yuki Fujita, Naoki Ookuma, Kazuki Yamauchi, Masahito Takehara, Toru Miwa
  • Patent number: 10840684
    Abstract: A link connects a corrugated tube to a box-shaped protector. The link includes an engagement portion capable of engaging with the corrugated tube, an attachment portion capable of attaching to the protector, and a projection piece projecting alongside the corrugated tube.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: November 17, 2020
    Assignee: YAZAKI CORPORATION
    Inventors: Akinori Yamauchi, Toru Kato
  • Patent number: 10711857
    Abstract: A bicycle disc brake rotor is basically provided with a main body and a heat release layer. The main body is made of a metallic material. The main body includes an outer portion, an inner portion and a cooling facilitation part. The outer portion has oppositely facing braking surfaces. The heat release layer includes a non-metallic material. The heat release layer at least partially overlies the cooling facilitation part.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: July 14, 2020
    Assignee: Shimano Inc.
    Inventors: Akio Nagai, Wataru Yamauchi, Toru Iwai
  • Publication number: 20200136359
    Abstract: A link connects a corrugated tube to a box-shaped protector. The link includes an engagement portion capable of engaging with the corrugated tube, an attachment portion capable of attaching to the protector, and a projection piece projecting alongside the corrugated tube.
    Type: Application
    Filed: September 23, 2019
    Publication date: April 30, 2020
    Applicant: Yazaki Corporation
    Inventors: Akinori YAMAUCHI, Toru KATO
  • Publication number: 20190264573
    Abstract: An acquisition unit is configured to acquire measurement values of a target device. The measurement values that are acquired include at least a temperature and a flow rate of an input fluid to be input to the target device, and a temperature and a flow rate of an output fluid to be output from the target device. A correction unit is configured to obtain a correction measurement value by which the measurement values are corrected through thermal equilibrium calculations based on the measurement values. A distance calculation unit is configured to calculate a Mahalanobis distance with a factor of the correction measurement value.
    Type: Application
    Filed: May 31, 2017
    Publication date: August 29, 2019
    Inventors: Ichiro NAGANO, Kuniaki AOYAMA, Mayumi SAITO, Shintaro KUMANO, Katsuhiko ABE, Toru TANAKA, Takahiro YAMAUCHI
  • Publication number: 20190197917
    Abstract: A guidance information presentation system includes an operation data collection unit configured to collect operation data of a plant, an operation mode determination unit configured to determine an operation mode of a plant device provided in the plant on the basis of the collected operation data, and a guidance information presentation unit configured to present guidance information according to the operation mode. Further, the guidance information presentation unit is configured to present the guidance information according to an operation state of the plant device or a department to which operating staff belongs.
    Type: Application
    Filed: October 11, 2017
    Publication date: June 27, 2019
    Inventors: Akihisa ENDO, Yui KANAMURA, Toru TANAKA, Takahiro YAMAUCHI, Hiroki SUGINO
  • Publication number: 20190187676
    Abstract: An acquisition unit is configured to acquire measurement values of a target device. A likelihood calculation unit is configured to calculate an occurrence likelihood for each of a plurality of phenomena that are liable to occur to the target device based on the measurement values acquired by the acquisition unit. A table storage unit is configured to store a table in which the plurality of phenomena and occurrence causes of abnormalities of the target device are associated to each other. As estimation unit is configured to estimate the occurrence causes based on the occurrence likelihood and the table.
    Type: Application
    Filed: May 31, 2017
    Publication date: June 20, 2019
    Inventors: Ichiro NAGANO, Kuniaki AOYAMA, Mayumi SAITO, Shintaro KUMANO, Katsuhiko ABE, Toru TANAKA, Takahiro YAMAUCHI
  • Patent number: 10326253
    Abstract: An optical module and a method of assembling the optical module are disclosed. The optical module comprises a laser unit, a modulator unit, and a detector unit mounted on respective thermo-electric coolers (TECs). The modulator unit, which is arranged on an optical axis of the first output port from which a modulated beam is output, modulates the continuous wave (CW) beam output from the laser unit. On the other hand, the laser unit and the detector unit are arranged on another optical axis of the second output port from which another CW beam is output. The method of assembling the optical module first aligns one of the first combination of the laser unit and the modulator unit with the first output port and the second combination of the laser unit and the detector unit, and then aligns another of the first combination and the second combination.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 18, 2019
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kazuhiro Yamaji, Yasushi Fujimura, Toru Watanabe, Yasuyuki Yamauchi, Tomoya Saeki, Munetaka Kurokawa
  • Patent number: 9810905
    Abstract: A support information display method is provided with an acquiring process for acquiring a first image by photographing, via a camera provided in a head mount display, a predetermined part of a substrate processing apparatus as a maintenance object, an estimating process for estimating the support information related to the predetermined part in the first image from information stored in a database, an image creating process for creating a second image by converting the support information estimated in the estimating process into an image, and a displaying process for displaying the second image on the head mount display in order for the operator to visually recognize the support information.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: November 7, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toshiaki Kodama, Toru Yamauchi, Sensho Kobayashi, Hiroshi Nakamura, Gaku Ikeda, Kazuya Uoyama
  • Patent number: 9620402
    Abstract: An alignment apparatus for aligning a wafer includes a mounting unit, an imaging unit, an elevation unit, and a controlling unit. The control unit outputs a control signal for controlling the elevation unit such that a luminance variation between the outer side and the inner side of the wafer obtained by the imaging unit becomes the same as a luminance variation obtained when the imaging unit is focused, for estimating a warpage state of the wafer based on an amount of relative movement of the imaging unit and the mounting unit with respect to a relative height position of the imaging unit and the mounting unit obtained when the imaging unit is focused on a reference wafer having no warpage, and for detecting the alignment mark of the wafer by the imaging unit by rotating the mounting unit in a state where the imaging unit is focused.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: April 11, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Toshiaki Kodama, Toru Yamauchi
  • Publication number: 20160078626
    Abstract: An alignment apparatus for aligning a wafer includes a mounting unit, an imaging unit, an elevation unit, and a controlling unit. The control unit outputs a control signal for controlling the elevation unit such that a luminance variation between the outer side and the inner side of the wafer obtained by the imaging unit becomes the same as a luminance variation obtained when the imaging unit is focused, for estimating a warpage state of the wafer based on an amount of relative movement of the imaging unit and the mounting unit with respect to a relative height position of the imaging unit and the mounting unit obtained when the imaging unit is focused on a reference wafer having no warpage, and for detecting the alignment mark of the wafer by the imaging unit by rotating the mounting unit in a state where the imaging unit is focused.
    Type: Application
    Filed: September 17, 2015
    Publication date: March 17, 2016
    Inventors: Toshiaki KODAMA, Toru YAMAUCHI
  • Publication number: 20140240484
    Abstract: A support information display method is provided with an acquiring process for acquiring a first image by photographing, via a camera provided in a head mount display, a predetermined part of a substrate processing apparatus as a maintenance object, an estimating process for estimating the support information related to the predetermined part in the first image from information stored in a database, an image creating process for creating a second image by converting the support information estimated in the estimating process into an image, and a displaying process for displaying the second image on the head mount display in order for the operator to visually recognize the support information.
    Type: Application
    Filed: February 6, 2014
    Publication date: August 28, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Toshiaki KODAMA, Toru YAMAUCHI, Sensho KOBAYASHI, Hiroshi NAKAMURA, Gaku IKEDA, Kazuya UOYAMA
  • Patent number: 7898798
    Abstract: A heat dissipating structure for an electronic component of the present invention includes a main board on which electronic components are mounted, a heat sink disposed facing the main board and contacting a plurality of the electronic components on the main board, a heat pipe disposed on the heat sink, an arm branching from the heat sink and elastically deformable in relation to the heat sink, and a cooling fan located at the end portion of the heat pipe.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: March 1, 2011
    Assignee: Sony Corporation
    Inventors: Tatsuya Sakata, Toru Yamauchi, Kenichi Seki, Terutaka Yana
  • Patent number: 7800895
    Abstract: An electronic apparatus includes a drive for recording/reproducing a recording medium, and a sound absorbing member having a Helmholtz resonator for insulating sounds at a predetermined frequency among sounds generated by the drive.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: September 21, 2010
    Assignee: Sony Corporation
    Inventors: Akira Inoue, Sumio Otsuka, Norio Kobayashi, Toru Yamauchi
  • Publication number: 20090141450
    Abstract: A heat dissipating structure for an electronic component of the present invention includes a main board on which electronic components are mounted, a heat sink disposed facing the main board and contacting a plurality of the electronic components on the main board, a heat pipe disposed on the heat sink, an arm branching from the heat sink and elastically deformable in relation to the heat sink, and a cooling fan located at the end portion of the heat pipe.
    Type: Application
    Filed: November 28, 2008
    Publication date: June 4, 2009
    Applicant: Sony Corporation
    Inventors: Tatsuya SAKATA, Toru YAMAUCHI, Kenichi SEKI, Terutaka YANA
  • Publication number: 20080078611
    Abstract: An electronic apparatus includes a drive for recording/reproducing a recording medium, and a sound absorbing member having a Helmholtz resonator for insulating sounds at a predetermined frequency among sounds generated by the drive.
    Type: Application
    Filed: September 13, 2007
    Publication date: April 3, 2008
    Applicant: Sony Corporation
    Inventors: Akira Inoue, Sumio Otsuka, Norio Kobayashi, Toru Yamauchi
  • Patent number: 6754554
    Abstract: An interlock system can discriminate a controller in which an abnormality occurs in a control system of a semiconductor manufacturing apparatus in which a plurality of controllers are connected through a network. A processing system contains at least one processing chamber which performs a semiconductor manufacturing process. A conveyance system takes an object to be processed in and out of the processing chamber. The control system includes at least one apparatus controller, which controls the processing system and the conveyance system, and an equipment controller, which manages the apparatus controller. The apparatus controller and the equipment controller are communicably connected through a network.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: June 22, 2004
    Assignee: Tokyo Electron Limited
    Inventors: Toru Yamauchi, Kiminori Okada, Tadahito Nezu
  • Publication number: 20030182012
    Abstract: An interlock system can discriminate a controller in which an abnormality occurs in a control system of a semiconductor manufacturing apparatus in which a plurality of controllers are connected through a network. A processing system contains at least one processing chamber which performs a semiconductor manufacturing process. A conveyance system takes an object to be processed in and out of the processing chamber. The control system includes at least one apparatus controller, which controls the processing system and the conveyance system, and an equipment controller, which manages the apparatus controller. The apparatus controller and the equipment controller are communicably connected through a network.
    Type: Application
    Filed: December 12, 2002
    Publication date: September 25, 2003
    Inventors: Toru Yamauchi, Kiminori Okada, Tadahito Nezu