Abstract: A method and apparatus for serial communication with a co-processor. In one embodiment, a microprocessor is provided with a CPU core, set of serial interface registers, a serial interface unit, to provide serial communication between a co-processor and the microprocessor. The set of serial interface registers is part of a register file of the CPU core and interrupts are exchanged between the CPU core and the co-processor to allow for reading and writing of data placed in the serial registers of the register file.

Abstract: A computer system includes a first processor, a second processor, and interprocessor communication logic (ICL). The first processor operates at a higher frequency, includes a more advanced micro-architecture, and consumes more power than the second processor. When the computer system is plugged in, the first processor is selected as the primary system processor. When the computer system is powered by a battery, the second processor is selected as the primary system processor. The second processor and the ICL may be integrated together on the same semiconductor chip.

Abstract: A system includes multiple program execution entities (e.g., tasks, processes, threads, and the like) and a cache memory having multiple sections. An identifier is assigned to each execution entity. An instruction of one of the execution entities is retrieved and an associated identifier is decoded. Information associated with the instruction is stored in one of the cache sections based on the identifier.

Abstract: A system includes multiple program execution entities (e.g., tasks, processes, threads, and the like) and a cache memory having multiple sections. An identifier is assigned to each execution entity. An instruction of one of the execution entities is retrieved and an associated identifier is decoded. Information associated with the instruction is stored in one of the cache sections based on the identifier.

Abstract: A system includes multiple program execution entities (e.g., tasks, processes, threads, and the like) and a cache memory having multiple sections. An identifier is assigned to each execution entity. An instruction of one of the execution entities is retrieved and an associated identifier is decoded. Information associated with the instruction is stored in one of the cache sections based on the identifier.

Abstract: A system includes multiple program execution entities (e.g., tasks, processes, threads, and the like) and a cache memory having multiple sections. An identifier is assigned to each execution entity. An instruction of one of the execution entities is retrieved and an associated identifier is decoded. Information associated with the instruction is stored in one of the cache sections based on the identifier.

Abstract: A method and apparatus for operating an integrated in a reduced-power consumption state are described. The apparatus comprises power-reduction logic which, to place the integrated circuit in the reduced-power consumption state, gates a clock signal to both first and second sets of functional units within the integrated circuit. The first set of functional units is distinguished in that it is required to perform cache coherency operations within integrated circuit. The apparatus includes an input which is coupled to receive a signal indicating a memory access, to a memory resource accessible by the integrated circuit, by a further device external to the integrated circuit. In response to the assertion of this signal, the power-reduction logic propagates the clock signal to the first set of functional units, to enable this set of functional units to perform a cache coherency operation which may be necessitated by the memory access by the external device.

Abstract: An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the/assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.

Abstract: An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.

Abstract: An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.

Abstract: An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.

Abstract: An apparatus and method for controlling the stopping of the clock signal utilized by the processing unit of a computer system comprises the use of a novel external pin which can be enabled to initiate a sequence of events that results in the halting of the internal clock signal. The invention includes a microcode engine that responds to the assertion of the external pin by executing a sequence of steps which stops the current instruction on an instruction boundary. A logic circuit then generates a signal that masks the clock signal produced by the system's phase-locked loop. An interrupt mechanism is also utilized to prioritize the occurrence of the external signal among other system interrupts. The interrupt mechanism insures that the processor never has its clock stopped in the middle of a bus cycle.

Abstract: A microprocessor for use in a computer system which pipelines addresses for both burst and non-burst mode data transfers. By pipelining addresses, the microprocessor is able to increase the throughput of data transfers in the system. In the present invention, bits are used which may be programmed to disable and enable the address pipelining for the non-burst mode and burst mode transfers.

Abstract: An electronic translator comprises a memory circuit for storing words which is removable from the translator, an attachment connectable to the translator, and a coupling device permitting either the memory circuit or the attachment to be connected to the translator. The coupling device is provided within the translator. The attachment may be a printer or an audible sound generator.

Abstract: A drive circuit is used to drive a data matrix liquid crystal display panel that can be applied to a variety of uses wherein said drive circuit either generates the backplate signal using any optional sequence or optionally provides any desired duty factor.The drive circuit chip itself contains RAM, and in responding to the data contents in said RAM, both the backplate and segment signals are generated, where the drive circuit provides any desired sequence that can optionally be determined in accordance with the RAM data contents.As an alternative embodiment of the present invention, the drive circuit chip comprises a built-in counter that determines the duty factor of the liquid crystal enable signals, where the duty factor can optionally be set by varying the operational conditions of said counter.

Abstract: An electronic translator comprises an input device for entering a first word or words, a first memory circuit for storing the first words, a second memory circuit for storing second words equivalent to the first words, an access circuit for addressing the memory circuits to cause retrieval of the first word or words, or alternately the second word or words, and a control circuit for controlling activation of the access circuit. There may be additionally provided a holding circuit for holding one or more of the first words without translation thereof.

Abstract: An electronic translator comprises an input device for entering a first word or words, a first memory circuit for storing the first words, a second memory circuit for storing second words equivalent to the first words, an access circuit for addressing the memory circuits to cause retrieval of the first word or words, or alternately the second word or words, and a control circuit for controlling activation of the access circuit. There may be additionally provided a holding circuit for holding one or more of the first words without translation thereof.

Abstract: An electronic translator comprising a first memory for providing signals representing a first word or words in a first language, a second memory for providing signals representing a second word or words in a second language, a first connector selectively occupied by at least one of the first and the second memories, a control device for processing the two types of signals, and carry out operations of the translator, and a second connector selectively occupied by the control device. Preferably, either of the first and the second memories is built into the body of the translator. A second control device may be built into the translator for processing the two types of signals and carrying out operations of the translator, in which case the two control devices are operable in the alternative to the exclusion of each other.

Abstract: A display drive especially for use with a liquid crystal display panel is disclosed herein, which avoids disturbance of the contents on display and ensures high degrees of commercial value and display quality of the display. The display drive prohibits operation of the display just after initial power application and thereafter allows the display to operate in normal manner. The display is responsive to the signal for use in data processing, no particular terminals are necessary on integrated circuit devices in receiving externally signals.

Abstract: An electronic translator is characterized in that a new translated sentence is prepared by using at least one word contained in a sentence key inputted those cases where no word corresponding to the word is stored in a memory for storing a plurality of translated words. The translator comprises an input circuit for inputting the sentence, an access circuit for accessing a most equivalent translated sentence, and a detection circuit for detecting whether all of the words contained in the sentence are stored in memory and for inserting such unstored words directly into the translated sentence.