Abstract: A flying body identification system according to the present example embodiment includes: a flying body; a communication terminal configured to obtain an airframe ID of the flying body; and a control system configured to control an operation of the flying body. The control system is also configured to: manage the airframe ID and a plurality of pieces of information regarding the flying body indicated by the airframe ID so as to be associated with each other; select, in a case where an inquiry message containing the airframe ID and an authority level assigned to the communication terminal is received from the communication terminal, information to be transmitted to the communication terminal among the plurality of pieces of information regarding the flying body associated with the airframe ID in accordance with the authority level of the communication terminal; and transmit the selected information to the communication terminal.

Abstract: An air traffic control system (31) according to the present disclosure includes a communication unit (4) configured to receive, from a communication terminal (40), an image including a flying object (2) captured by the communication terminal (40) and position information about the communication terminal (40), an estimation unit (8) configured to estimate a position of the flying object (2) using background information and the position information included in the image, and an identification unit (5) configured to identify the flying object (2) using the estimated position of the flying object (2). The communication unit (4) transmits information about the identified flying object (2) to the communication terminal (40).

Abstract: A flying object according to example embodiments includes an airframe ID control unit configured to hold an airframe ID of the flying object changed according to a predetermined change pattern, and a communication unit configured to transmit the airframe ID. An air traffic control system according to the example embodiments includes a communication unit configured to acquire a first airframe ID and position information transmitted from a flying object, and an identification unit configured to identify the flying object using the first airframe ID. When the communication unit acquires a second airframe ID different from the first airframe ID after acquiring the first airframe ID, the identification unit determines whether or not the second airframe ID indicates the flying object based on a change between the position information at the time of acquiring the first airframe ID and the position information at the time of acquiring the second airframe ID.

Abstract: A problem to be solved by the present invention is to provide a magnetic recording medium having a jet-black magnetic stripe which is not tinged with red. The present invention is directed to a magnetic recording medium including: a magnetic recording layer on a substrate; and a protective layer (a) on the magnetic recording layer, wherein the protective layer (a) contains an aniline coloring material. The magnetic recording medium is advantageous in that the magnetic stripe is jet-black and has excellent design properties, and therefore can be widely used for credit cards, bank cards and the like.

Abstract: A problem to be solved by the present invention is to provide a magnetic recording medium having a jet-black magnetic stripe which is not tinged with red. The present invention is directed to a magnetic recording medium including: a magnetic recording layer on a substrate; and a protective layer (a) on the magnetic recording layer, wherein the protective layer (a) contains an aniline coloring material. The magnetic recording medium is advantageous in that the magnetic stripe is jet-black and has excellent design properties, and therefore can be widely used for credit cards, bank cards and the like.

Abstract: Provided is a piston temperature state monitoring system for an internal combustion engine and a piston temperature monitoring method for an internal combustion engine which are capable of properly managing a history of a piston temperature. When the number of times of a piston temperature suppression control is counted, if a ratio of a temperature difference which is the difference between a maximum limit temperature and a piston temperature to a margin width which is the difference between the maximum limit temperature and a control start temperature is equal to or less than a count threshold ratio set in advance or calculated, a count output system outputs a count signal.

Abstract: Provided is a piston temperature state monitoring system for an internal combustion engine and a piston temperature monitoring method for an internal combustion engine which are capable of properly managing a history of a piston temperature. When the number of times of a piston temperature suppression control is counted, if a ratio of a temperature difference which is the difference between a maximum limit temperature and a piston temperature to a margin width which is the difference between the maximum limit temperature and a control start temperature is equal to or less than a count threshold ratio set in advance or calculated, a count output system outputs a count signal.

Abstract: In order to efficiently test a plurality of types of devices under test, provided is a test apparatus that tests a device under test, comprising one or more test modules that each include a plurality of testing sections testing the device under test by exchanging signals with the device under test; and a plurality of control apparatuses that control operation of the testing sections. In each of the one or more test modules, the plurality of testing sections are each allocated to one of the plurality of control apparatuses, and each of the control apparatuses is capable of executing a test program managed by a different user, and controls operation of the testing sections allocated thereto.

Abstract: In order to efficiently test a plurality of types of devices under test, provided is a test apparatus that tests a device under test, comprising one or more test modules that each include a plurality of testing sections testing the device under test by exchanging signals with the device under test; and a plurality of control apparatuses that control operation of the testing sections. In each of the one or more test modules, the plurality of testing sections are each allocated to one of the plurality of control apparatuses, and each of the control apparatuses is capable of executing a test program managed by a different user, and controls operation of the testing sections allocated thereto.

Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.

Abstract: Method and system for associating software components with vendor hardware module versions in an open architecture test system are disclosed. The method includes receiving a set of hardware versions of a vendor hardware module, receiving a set of software components supported by the vendor hardware module, processing the set of hardware versions, where the set of hardware versions is represented as an equivalence class of hardware version numbers using a mask value, obtaining user choices of hardware versions of the vendor hardware module, validating the user choices of hardware versions of the vendor hardware module, and creating a system profile in accordance with the user choices of hardware versions.

Abstract: A method for managing multiple hardware test module versions, software components, and tester operating system (TOS) versions in a modular test system is disclosed. The method includes installing the TOS versions compatible with the modular test system in an archive and installing vendor software components corresponding to the hardware test module versions in the archive. The method further includes creating system profiles for describing vendor software components corresponding to the hardware test module versions and the TOS versions, selecting a system profile for the modular test system, where the system profile includes a set of compatible vendor software components and a selected TOS for testing a particular hardware test module version, and activating the selected TOS on the modular test system.

Abstract: Provided is a test apparatus 10, which includes: a plurality of test modules 150, each of which is connected to any of the plurality of devices under test 100 to supply a test signal to the connected device under test 100; a plurality of site controllers 130 that control the plurality of test modules 150 to test the respective plurality of devices under test 100 simultaneously; a connection setting device 140 that sets a connection mode between the plurality of site controllers 130 and the plurality of test modules 150 so that each of the test modules 150 is connected to any of the plurality of site controllers 130; and a plurality of system controllers 110, each of which controls any of the plurality of site controllers 130, in which a predetermined system controller of the plurality of system controllers 110 assigns, in response to a request from another system controller of the system controllers, a site controller of the site controllers, which is to be controlled by the another system controller.

Abstract: Test equipment includes a memory to which a test plan that includes a plurality of sub-test plans is loaded and a system controller that, when the test equipment actually examines a device-under-test (DUT), loads the test plan to the memory by the unit of the sub-test plan and supplies a test signal to the DUT by interpreting the loaded test plan.

Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.

Abstract: Provided is a test apparatus 10, which includes: a plurality of test modules 150, each of which is connected to any of the plurality of devices under test 100 to supply a test signal to the connected device under test 100; a plurality of site controllers 130 that control the plurality of test modules 150 to test the respective plurality of devices under test 100 simultaneously; a connection setting device 140 that sets a connection mode between the plurality of site controllers 130 and the plurality of test modules 150 so that each of the test modules 150 is connected to any of the plurality of site controllers 130; and a plurality of system controllers 110, each of which controls any of the plurality of site controllers 130, in which a predetermined system controller of the plurality of system controllers 110 assigns, in response to a request from another system controller of the system controllers, a site controller of the site controllers, which is to be controlled by the another system controller.

Abstract: An efficient and low-cost method for testing multiple DUTs in a parallel test system is disclosed. In one embodiment, a method for scheduling tests in a parallel test system having at least two devices-under-test (DUTs) coupled to a test controller through one or more vendor hardware modules includes receiving a test plan comprising a plurality of tests arranged in a predetermined test flow, where the predetermined test flow comprises a plurality of tests arranged in a directed graph and each test is arranged as a vertex in the directed graph, determining a test execution schedule in accordance with the test plan at runtime, where the test execution schedule identifies a set of next tests to be executed according to current states of the at least two DUTs and where the set of next tests include different tests to be performed on different DUTs, and testing the at least two DUTs using the test execution schedule.

Abstract: The test equipment includes a memory to which a test plan consisting of a plurality of sub-test plans is loaded; and a controller that loads the test plan to the memory by the unit of the sub-test plan and supplies a test signal to the DUT by interpreting the loaded test plan.

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of