Patents by Inventor Toshiaki Adachi

Toshiaki Adachi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190212304
    Abstract: An inspection operator can perform a hammering inspection without operation to move an inspection device to a location to be inspected, and the hammering inspection can also be performed to the location to be inspected where a vehicle has difficulty in entering. An inspection system includes a flying device including a hammering inspection unit that performs an inspection and a flying unit that flies with the hammering inspection unit, a ground-side device that is fixedly installed at a position relative to a location to be inspected and detects a position of the flying device, and a flight instruction unit that controls the flying device in such a way that a forwarding direction of the flying device is a direction from the ground-side device to the location to be inspected based on the position of the flying device.
    Type: Application
    Filed: May 17, 2017
    Publication date: July 11, 2019
    Applicant: NEC Corporation
    Inventors: Toshiaki YAMASHITA, Hideo ADACHI, Michitaro SHOZAWA
  • Patent number: 9342425
    Abstract: In order to efficiently test a plurality of types of devices under test, provided is a test apparatus that tests a device under test, comprising one or more test modules that each include a plurality of testing sections testing the device under test by exchanging signals with the device under test; and a plurality of control apparatuses that control operation of the testing sections. In each of the one or more test modules, the plurality of testing sections are each allocated to one of the plurality of control apparatuses, and each of the control apparatuses is capable of executing a test program managed by a different user, and controls operation of the testing sections allocated thereto.
    Type: Grant
    Filed: March 27, 2012
    Date of Patent: May 17, 2016
    Assignee: ADVANTEST CORPORATION
    Inventors: Takeshi Yaguchi, Hajime Sugimura, Takahiro Nakajima, Toshiaki Adachi
  • Publication number: 20130231886
    Abstract: In order to efficiently test a plurality of types of devices under test, provided is a test apparatus that tests a device under test, comprising one or more test modules that each include a plurality of testing sections testing the device under test by exchanging signals with the device under test; and a plurality of control apparatuses that control operation of the testing sections. In each of the one or more test modules, the plurality of testing sections are each allocated to one of the plurality of control apparatuses, and each of the control apparatuses is capable of executing a test program managed by a different user, and controls operation of the testing sections allocated thereto.
    Type: Application
    Filed: March 27, 2012
    Publication date: September 5, 2013
    Applicant: ADVANTEST CORPORATION
    Inventors: Takeshi YAGUCHI, Hajime SUGIMURA, Takahiro NAKAJIMA, Toshiaki ADACHI
  • Patent number: 8255198
    Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: August 28, 2012
    Assignee: Advantest Corporation
    Inventors: Ramachandran Krishnaswamy, Harsanjeet Singh, Ankan Pramanick, Mark Elston, Leon Chen, Toshiaki Adachi, Yoshihumi Tahara
  • Patent number: 8214800
    Abstract: Method and system for associating software components with vendor hardware module versions in an open architecture test system are disclosed. The method includes receiving a set of hardware versions of a vendor hardware module, receiving a set of software components supported by the vendor hardware module, processing the set of hardware versions, where the set of hardware versions is represented as an equivalence class of hardware version numbers using a mask value, obtaining user choices of hardware versions of the vendor hardware module, validating the user choices of hardware versions of the vendor hardware module, and creating a system profile in accordance with the user choices of hardware versions.
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: July 3, 2012
    Assignee: Advantest Corporation
    Inventors: Ankan Pramanick, Mark Elston, Toshiaki Adachi
  • Patent number: 8082541
    Abstract: A method for managing multiple hardware test module versions, software components, and tester operating system (TOS) versions in a modular test system is disclosed. The method includes installing the TOS versions compatible with the modular test system in an archive and installing vendor software components corresponding to the hardware test module versions in the archive. The method further includes creating system profiles for describing vendor software components corresponding to the hardware test module versions and the TOS versions, selecting a system profile for the modular test system, where the system profile includes a set of compatible vendor software components and a selected TOS for testing a particular hardware test module version, and activating the selected TOS on the modular test system.
    Type: Grant
    Filed: April 5, 2005
    Date of Patent: December 20, 2011
    Assignee: Advantest Corporation
    Inventors: Ankan Pramanick, Jim Hanrahan, Mark Elston, Toshiaki Adachi, Leon L. Chen
  • Patent number: 8078424
    Abstract: Provided is a test apparatus 10, which includes: a plurality of test modules 150, each of which is connected to any of the plurality of devices under test 100 to supply a test signal to the connected device under test 100; a plurality of site controllers 130 that control the plurality of test modules 150 to test the respective plurality of devices under test 100 simultaneously; a connection setting device 140 that sets a connection mode between the plurality of site controllers 130 and the plurality of test modules 150 so that each of the test modules 150 is connected to any of the plurality of site controllers 130; and a plurality of system controllers 110, each of which controls any of the plurality of site controllers 130, in which a predetermined system controller of the plurality of system controllers 110 assigns, in response to a request from another system controller of the system controllers, a site controller of the site controllers, which is to be controlled by the another system controller.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: December 13, 2011
    Assignee: Advantest Corporation
    Inventor: Toshiaki Adachi
  • Patent number: 7809520
    Abstract: Test equipment includes a memory to which a test plan that includes a plurality of sub-test plans is loaded and a system controller that, when the test equipment actually examines a device-under-test (DUT), loads the test plan to the memory by the unit of the sub-test plan and supplies a test signal to the DUT by interpreting the loaded test plan.
    Type: Grant
    Filed: November 5, 2007
    Date of Patent: October 5, 2010
    Assignee: Advantest Corporation
    Inventor: Toshiaki Adachi
  • Publication number: 20100192135
    Abstract: Test program development for a semiconductor test system, such as automated test equipment (ATE), using object-oriented constructs is described. The invention provides a method for describing test system resources, test system configuration, module configuration, test sequence, test plan, test condition, test pattern, and timing information in general-purpose object-oriented constructs, e.g., C++ objects and classes. In particular, the modularity of program development is suitable for developing test programs for an open architecture semiconductor test system.
    Type: Application
    Filed: March 26, 2010
    Publication date: July 29, 2010
    Applicant: Advantest Corporation
    Inventors: Ramachandran KRISHNASWAMY, Harsanjeet SINGH, Ankan PRAMANICK, Mark ELSTON, Leon CHEN, Toshiaki ADACHI, Yoshihumi TAHARA
  • Publication number: 20100082284
    Abstract: Provided is a test apparatus 10, which includes: a plurality of test modules 150, each of which is connected to any of the plurality of devices under test 100 to supply a test signal to the connected device under test 100; a plurality of site controllers 130 that control the plurality of test modules 150 to test the respective plurality of devices under test 100 simultaneously; a connection setting device 140 that sets a connection mode between the plurality of site controllers 130 and the plurality of test modules 150 so that each of the test modules 150 is connected to any of the plurality of site controllers 130; and a plurality of system controllers 110, each of which controls any of the plurality of site controllers 130, in which a predetermined system controller of the plurality of system controllers 110 assigns, in response to a request from another system controller of the system controllers, a site controller of the site controllers, which is to be controlled by the another system controller.
    Type: Application
    Filed: September 29, 2008
    Publication date: April 1, 2010
    Applicant: ADVANTEST CORPORATION
    Inventor: Toshiaki Adachi
  • Patent number: 7543200
    Abstract: An efficient and low-cost method for testing multiple DUTs in a parallel test system is disclosed. In one embodiment, a method for scheduling tests in a parallel test system having at least two devices-under-test (DUTs) coupled to a test controller through one or more vendor hardware modules includes receiving a test plan comprising a plurality of tests arranged in a predetermined test flow, where the predetermined test flow comprises a plurality of tests arranged in a directed graph and each test is arranged as a vertex in the directed graph, determining a test execution schedule in accordance with the test plan at runtime, where the test execution schedule identifies a set of next tests to be executed according to current states of the at least two DUTs and where the set of next tests include different tests to be performed on different DUTs, and testing the at least two DUTs using the test execution schedule.
    Type: Grant
    Filed: February 17, 2005
    Date of Patent: June 2, 2009
    Assignee: Advantest Corporation
    Inventors: Ankan Pramanick, Toshiaki Adachi, Mark Elston
  • Publication number: 20090119054
    Abstract: The test equipment includes a memory to which a test plan consisting of a plurality of sub-test plans is loaded; and a controller that loads the test plan to the memory by the unit of the sub-test plan and supplies a test signal to the DUT by interpreting the loaded test plan.
    Type: Application
    Filed: November 5, 2007
    Publication date: May 7, 2009
    Applicant: ADVANTEST CORPORATION
    Inventor: Toshiaki Adachi
  • Publication number: 20080016396
    Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of
    Type: Application
    Filed: September 24, 2007
    Publication date: January 17, 2008
    Applicant: ADVANTEST CORPORATION
    Inventors: Shinsaku Higashi, Seiji Ichiyoshi, Ankan Pramanick, Mark Elston, Leon Chen, Robert Sauer, Ramachandran Krishnaswamy, Harsanjeet Singh, Toshiaki Adachi, Yoshihumi Tahara
  • Publication number: 20080010524
    Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of
    Type: Application
    Filed: September 24, 2007
    Publication date: January 10, 2008
    Applicant: ADVANTEST CORPORATION
    Inventors: Shinsaku Higashi, Seiji Ichiyoshi, Ankan Pramanick, Mark Elston, Leon Chen, Robert Sauer, Ramachandran Krishnaswamy, Harsanjeet Singh, Toshiaki Adachi, Yoshihumi Tahara
  • Patent number: 7210087
    Abstract: A method for simulating a modular test system is disclosed. The method includes providing a controller, where the controller controls at least one vendor module and its corresponding device under test (DUT) model, creating a simulation framework for establishing standard interfaces between the at least one vendor module and its corresponding DUT model, configuring the simulation framework, and simulating the modular test system using the simulation framework.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: April 24, 2007
    Assignee: Advantest America R&D Center, Inc.
    Inventors: Conrad Mukai, Ankan Pramanick, Mark Elston, Toshiaki Adachi, Leon L. Chen
  • Patent number: 7209851
    Abstract: A method for managing a pattern object file in a modular test system is disclosed. The method includes providing a modular test system, where the modular test system comprises a system controller for controlling at least one site controller, and where the at least one site controller controls at least one test module and its corresponding device under test (DUT). The method further includes creating an object file management framework for establishing a standard interface between vendor-supplied pattern compilers and the modular test system, receiving a pattern source file, creating a pattern object metafile based on the pattern source file using the object file management framework, and testing the device under test through the test module using the pattern object metafile.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: April 24, 2007
    Assignee: Advantest America R&D Center, Inc.
    Inventors: Harsanjeet Singh, Ankan Pramanick, Mark Elston, Yoshifumi Tahara, Toshiaki Adachi
  • Patent number: 7197417
    Abstract: A method for developing a test program for a semiconductor test system is disclosed. The method includes describing a test plan file in a test program language (TPL), where the test plan file describes at least one test of the test program, describing a test class file in a system program language (SPL) and a corresponding pre-header file of the test class file in the TPL, where the test class file describes an implementation of the at least one test of the test program, and generating the test program using the test plan file, the test class file, and the pre-header file.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: March 27, 2007
    Assignee: Advantest America R&D Center, Inc.
    Inventors: Ankan Pramanick, Mark Elston, Ramachandran Krishnaswamy, Toshiaki Adachi
  • Patent number: 7197416
    Abstract: A method for integrating test modules in a modular test system includes creating component categories for integrating vendor-supplied test modules and creating a calibration and diagnostics (C&D) framework for establishing a standard interface between the vendor-supplied test modules and the modular test system, where the C&D framework comprises interface classes communicating vendor-supplied module integration information. The method further includes receiving a vendor-supplied test module, retrieving module integration information from the vendor-supplied test module in accordance with the component categories, and integrating the vendor-supplied test module into the modular test system based on the module integration information using the C&D framework.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: March 27, 2007
    Assignee: Advantest America R&D Center, Inc.
    Inventors: Toshiaki Adachi, Ankan Pramanick, Mark Elston
  • Patent number: 7184917
    Abstract: A method for integrating test modules in a modular test system is disclosed. The method includes controlling at least one test module and its corresponding device under test (DUT) with a controller, establishing a standard module control interface between a vendor-supplied test module and the modular test system with a module control framework, installing the vendor-supplied test module and a corresponding vendor-supplied control software module, where the vendor-supplied control software module is organized into a plurality of vendor-supplied module control components, configuring the modular test system based on the module control framework and the plurality of vendor-supplied module control components, and accessing the vendor-supplied test module in accordance with the plurality of vendor-supplied module control components using the module control framework.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: February 27, 2007
    Assignee: Advantest America R&D Center, Inc.
    Inventors: Ankan Pramanick, Mark Elston, Toshiaki Adachi
  • Publication number: 20060200816
    Abstract: Method and system for associating software components with vendor hardware module versions in an open architecture test system are disclosed. The method includes receiving a set of hardware versions of a vendor hardware module, receiving a set of software components supported by the vendor hardware module, processing the set of hardware versions, where the set of hardware versions is represented as an equivalence class of hardware version numbers using a mask value, obtaining user choices of hardware versions of the vendor hardware module, validating the user choices of hardware versions of the vendor hardware module, and creating a system profile in accordance with the user choices of hardware versions.
    Type: Application
    Filed: March 2, 2005
    Publication date: September 7, 2006
    Applicant: Advantest America R&D Center, Inc.
    Inventors: Ankan Pramanick, Mark Elston, Toshiaki Adachi