Patents by Inventor Toshiaki Iwamatsu

Toshiaki Iwamatsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070034952
    Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
    Type: Application
    Filed: July 27, 2006
    Publication date: February 15, 2007
    Applicant: RENESAS TECHNOLOGY CORP.
    Inventors: Shigenobu Maeda, Toshiaki Iwamatsu, Takashi Ipposhi
  • Publication number: 20070032001
    Abstract: The present invention provides a method of fabricating a semiconductor device in which deterioration in a transistor characteristic is prevented by preventing a channel stop implantation layer from being formed in an active region. A resist mask is formed so as to have an opening over a region in which a PMOS transistor is formed. Channel stop implantation is performed with energy by which ions pass through a partial isolation oxide film and a peak of an impurity profile is generated in an SOI layer, thereby forming a channel stop layer in the SOI layer under the partial isolation oxide film, that is, an isolation region. An impurity to be implanted here is an N-type impurity. In the case of using phosphorus, its implantation energy is set to, for example, 60 to 120 keV, and the density of the channel stop layer is set to 1×1017 to 1×1019/cm3. At this time, the impurity of channel stop implantation is not stopped in the SOI layer corresponding to the active region.
    Type: Application
    Filed: October 5, 2006
    Publication date: February 8, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Takuji Matsumoto, Shigenobu Maeda
  • Patent number: 7173319
    Abstract: Plural trench isolation films (4) are provided with portions of an SOI layer (3) interposed therebetween in a surface of the SOI layer (3) in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element (30) are formed on the trench isolation films (4), respectively. Each of the trench isolation films (4) includes a central portion which passes through the SOI layer (3) and reaches a buried oxide film (2) to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer (3) and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films (4) includes a hybrid-trench isolation structure.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: February 6, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi
  • Publication number: 20060289904
    Abstract: In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer in the SOI layer formed on the buried oxide film layer (BOX layer). An isolation insulating layer is a partial trench isolation which has not reached a BOX layer, and source and drain regions include the first and the second impurity ion which differs in a mass number mutually.
    Type: Application
    Filed: June 19, 2006
    Publication date: December 28, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Mikio Tsujiuchi, Toshiaki Iwamatsu, Takashi Ipposhi
  • Publication number: 20060273394
    Abstract: A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).
    Type: Application
    Filed: August 14, 2006
    Publication date: December 7, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Hirokazu Sayama, Shigenobu Maeda, Toshiaki Iwamatsu, Kazunobu Ota
  • Patent number: 7144764
    Abstract: The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: December 5, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Mikio Tsujiuchi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Shigeto Maegawa
  • Publication number: 20060267012
    Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
    Type: Application
    Filed: August 4, 2006
    Publication date: November 30, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
  • Publication number: 20060270126
    Abstract: Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive elements are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer 3 to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.
    Type: Application
    Filed: August 8, 2006
    Publication date: November 30, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi
  • Publication number: 20060249756
    Abstract: A semiconductor device includes a plurality of circuit portions of different functions each constructed by including a MOS transistor on an SOI substrate obtained by sequentially stacking a semiconductor substrate, a buried insulating film and a semiconductor layer. The semiconductor device includes first and second portions. The first circuit portion is isolated by being surrounded with a first insulating film provided on an upper portion of the semiconductor layer and a second insulating film penetrating the semiconductor layer to reach the buried insulating film.
    Type: Application
    Filed: July 7, 2006
    Publication date: November 9, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Mikio Tsujiuchi, Toshiaki Iwamatsu, Shigenobu Maeda, Yuuichi Hirano, Shigeto Maegawa
  • Publication number: 20060244064
    Abstract: Formed on an insulator (9) are an N? type semiconductor layer (10) having a partial isolator formed on its surface and a P? type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).
    Type: Application
    Filed: June 8, 2006
    Publication date: November 2, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu
  • Publication number: 20060237726
    Abstract: While improving the frequency characteristics of a decoupling capacitor, suppressing the voltage drop of a source line and stabilizing it, the semiconductor device which suppressed decline in the area efficiency of decoupling capacitor arrangement is offered. Decoupling capacitors DM1 and DM2 are connected between the source line connected to the pad for high-speed circuits which supplies electric power to circuit block C1, and the ground line connected to a ground pad, and the capacitor array for high-speed circuits is formed. A plurality of decoupling capacitor DM1 are connected between the source line connected to the pad for low-speed circuits which supplies electric power to circuit block C2, and the ground line connected to a ground pad, and the capacitor array for low-speed circuits is formed. Decoupling capacitor DM1 differs in the dimension of a gate electrode from DM2.
    Type: Application
    Filed: April 24, 2006
    Publication date: October 26, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Toshiaki Iwamatsu, Takashi Ipposhi, Tatsuhiko Ikeda, Shigeto Maegawa
  • Patent number: 7112854
    Abstract: Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.
    Type: Grant
    Filed: May 2, 1997
    Date of Patent: September 26, 2006
    Assignee: Renesas Technology Corporation
    Inventors: Shigeto Maegawa, Takashi Ipposhi, Toshiaki Iwamatsu, Shigenobu Maeda, Il-Jung Kim, Kazuhito Tsutsumi, Hirotada Kuriyama, Yoshiyuki Ishigaki, Motomu Ukita, Toshiaki Tsutsumi
  • Patent number: 7109553
    Abstract: A semiconductor device which achieves reductions in malfunctions and operating characteristic variations by reducing the gain of a parasitic bipolar transistor, and a method of manufacturing the same are provided. A silicon oxide film (6) is formed partially on the upper surface of a silicon layer (3). A gate electrode (7) of polysilicon is formed partially on the silicon oxide film (6). A portion of the silicon oxide film (6) underlying the gate electrode (7) functions as a gate insulation film. A silicon nitride film (9) is formed on each side surface of the gate electrode (7), with a silicon oxide film (8) therebetween. The silicon oxide film (8) and the silicon nitride film (9) are formed on the silicon oxide film (6). The width (W1) of the silicon oxide film (8) in a direction of the gate length is greater than the thickness (T1) of the silicon oxide film (6).
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: September 19, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Hirokazu Sayama, Shigenobu Maeda, Toshiaki Iwamatsu, Kazunobu Ota
  • Patent number: 7105389
    Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51< prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: September 12, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Shigenobu Maeda, Toshiaki Iwamatsu, Takashi Ipposhi
  • Publication number: 20060186474
    Abstract: It is an object to provide a semiconductor device having an SOI structure in which an electric potential of a body region in an element formation region isolated by a partial isolation region can be fixed with a high stability. A MOS transistor comprising a source region (51), a drain region (61) and an H gate electrode (71) is formed in an element formation region isolated by a partial oxide film (31). The H gate electrode (71) electrically isolates a body region (13) formed in a gate width W direction adjacently to the source region (51) and the drain region (61) from the drain region (61) and the source region (51) through “I” in a transverse direction (a vertical direction in the drawing), a central “?” functions as a gate electrode of an original MOS transistor.
    Type: Application
    Filed: April 21, 2006
    Publication date: August 24, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Shigenobu Maeda, Toshiaki Iwamatsu, Takashi Ipposhi
  • Publication number: 20060180861
    Abstract: In a semiconductor device, a gate electrode, an impurity diffused region, a body potential fixing region, a first insulator, and a dummy gate electrode are provided on top of an SOI substrate consisting of an underlying silicon substrate, a buried insulator, and a semiconductor layer. The impurity diffused region is a region formed by implanting an impurity of a first conductivity type into the semiconductor layer around the gate electrode. The body potential fixing region is a region provided in the direction of an extension line of the length of the gate electrode and implanted with an impurity of a second conductivity type. The first insulator is formed at least in the portion between the body potential fixing region and the gate electrode. The dummy gate electrode is provided on the first insulator between the body potential fixing region and the gate electrode.
    Type: Application
    Filed: January 30, 2006
    Publication date: August 17, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Mikio Tsujiuchi, Toshiaki Iwamatsu, Shigeto Maegawa
  • Patent number: 7078767
    Abstract: Formed on an insulator (9) are an N? type semiconductor layer (10) having a partial isolator formed on its surface and a P? type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).
    Type: Grant
    Filed: November 17, 2003
    Date of Patent: July 18, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Takashi Ipposhi, Toshiaki Iwamatsu
  • Patent number: 7067881
    Abstract: A semiconductor device and its manufacturing method are provided which can properly avoid reduction of isolation breakdown voltage without involving adverse effects like an increase in junction capacitance. Impurity-introduced regions (11) are formed after a silicon layer (3) has been thinned through formation of recesses (14). Therefore n-type impurities are not implanted into the portions of the p-type silicon layer (3) that are located between the bottoms of element isolation insulating films (5) and the top surface of a BOX layer (2), which avoids reduction of isolation breakdown voltage. Furthermore, since the impurity-introduced regions (11) are formed to reach the upper surface of the BOX layer (2), the junction capacitance of source/drain regions (12) is not increased.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: June 27, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Takuji Matsumoto, Takashi Ipposhi, Toshiaki Iwamatsu, Yuuichi Hirano
  • Publication number: 20060134843
    Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.
    Type: Application
    Filed: December 27, 2005
    Publication date: June 22, 2006
    Applicant: Renesas Technology Corp.
    Inventors: Shigenobu Maeda, Takuji Matsumoto, Toshiaki Iwamatsu, Takashi Ipposhi
  • Patent number: 7053451
    Abstract: In formation of a source/drain region of an NMOS transistor, a gate-directional extension region <41a> of an N+ block region <41> in an N+ block resist film <51> prevents a well region <11> located under the gate-directional extension region <41a> from implantation of an N-type impurity. A high resistance forming region, which is the well region <11> having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode <9>, can be formed as a high resistance forming region <A2> narrower than a conventional high resistance forming region <A1>. Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: May 30, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Shigenobu Maeda, Toshiaki Iwamatsu, Takashi Ipposhi