Patents by Inventor Toshifumi Hashimoto

Toshifumi Hashimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240099031
    Abstract: A memory plane region includes a first structure and a second structure having conductive layers, and includes a first memory region to a third memory region, a first region between the first memory region and the second memory region, and a second region between the second memory region and the third memory region. The first structure comprises first via contact electrodes in the first region. The second structure comprises second via contact electrodes in the second region. The first via contact electrodes are electrically connected to transistors provided at positions where the first structure and the first region overlap, and where the second structure and the first region overlap. The second via contact electrodes are electrically connected to transistors provided at positions where the first structure and the second region overlap, and where the second structure and the second region overlap.
    Type: Application
    Filed: May 25, 2023
    Publication date: March 21, 2024
    Applicant: KIOXIA CORPORATION
    Inventor: Toshifumi HASHIMOTO
  • Patent number: 11929352
    Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: March 12, 2024
    Assignee: Kioxia Corporation
    Inventors: Hiroshi Maejima, Toshifumi Hashimoto, Takashi Maeda, Masumi Saitoh, Tetsuaki Utsumi
  • Publication number: 20240081065
    Abstract: A semiconductor memory device includes a substrate, a plurality of first conductive layers, a second conductive layer disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers, a first semiconductor column, a first electric charge accumulating film, a first wiring disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers and the second conductive layer, a first contact that is disposed between one end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring, and a second contact that is disposed between another end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring.
    Type: Application
    Filed: November 7, 2023
    Publication date: March 7, 2024
    Applicant: KIOXIA CORPORATION
    Inventor: Toshifumi HASHIMOTO
  • Patent number: 11856774
    Abstract: A semiconductor memory device includes a substrate, a plurality of first conductive layers, a second conductive layer disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers, a first semiconductor column, a first electric charge accumulating film, a first wiring disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers and the second conductive layer, a first contact that is disposed between one end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring, and a second contact that is disposed between another end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: December 26, 2023
    Assignee: Kioxia Corporation
    Inventor: Toshifumi Hashimoto
  • Publication number: 20230307016
    Abstract: A first conductor extends along first and second axes. A first memory pillar is provided in the first conductor and includes a first semiconductor and a charge accumulation layer. A second conductor extends along the second axis and is in contact with the first memory pillar. A third conductor extends along the first and second axes and is arranged with a distance from the first conductor along the second axis. A second memory pillar is provided in the third conductor and includes a second semiconductor and a charge accumulation layer. The fourth conductor extends along the second axis and is in contact with the second memory pillar. The fifth conductor extends along the second axis and is coupled to the first and second memory pillars.
    Type: Application
    Filed: June 20, 2022
    Publication date: September 28, 2023
    Applicant: Kioxia Corporation
    Inventors: Hiroshi Maejima, Toshifumi Hashimoto
  • Patent number: 11728267
    Abstract: A semiconductor memory device is provided that includes a plurality of memory blocks, arranged in a second direction, that are spaced from a semiconductor substrate in a first direction intersecting with a surface of the semiconductor substrate; a first wiring that is farther from the semiconductor substrate than the plurality of memory blocks in the first direction; a second wiring that is closer to the semiconductor substrate than the plurality of memory blocks in the first direction; a first contact; a first transistor with a first active region disposed in the semiconductor substrate, the second wiring being electrically connected to a first memory block among the plurality of memory blocks via the first transistor; and a second transistor where the second wiring being electrically connected to a second memory block among the plurality of memory blocks via the second transistor.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: August 15, 2023
    Assignee: Kioxia Corporation
    Inventors: Toshifumi Hashimoto, Jumpei Sato
  • Publication number: 20230074030
    Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.
    Type: Application
    Filed: November 10, 2022
    Publication date: March 9, 2023
    Inventors: Hiroshi MAEJIMA, Toshifumi HASHIMOTO, Takashi MAEDA, Masumi SAITOH, Tetsuaki UTSUMI
  • Patent number: 11538791
    Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: December 27, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Hiroshi Maejima, Toshifumi Hashimoto, Takashi Maeda, Masumi Saitoh, Tetsuaki Utsumi
  • Publication number: 20220319590
    Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.
    Type: Application
    Filed: June 22, 2022
    Publication date: October 6, 2022
    Inventors: Tomoki NAKAGAWA, Koji KATO, Toshifumi HASHIMOTO
  • Patent number: 11441257
    Abstract: The present disclosure relates to a clothes dryer capable of reducing pressure loss of air due to a lint removal device. The clothes dryer includes a case, a drum rotatably supported inside the case, an air supply port configured to guide air into the drum, an exhaust port configured to guide air inside the drum to the outside of the drum, an exhaust duct configured to guide air passed through the exhaust port to the air supply port, a connecting duct connecting the exhaust port and the exhaust duct, and a lint removal device configured to remove lint in the air passed through the exhaust port, wherein the lint removal device is disposed inside the exhaust duct and configured to communicate with the connecting duct.
    Type: Grant
    Filed: November 23, 2018
    Date of Patent: September 13, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenori Hato, Toshifumi Hashimoto, Hitoshi Minai
  • Patent number: 11393525
    Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: July 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tomoki Nakagawa, Koji Kato, Toshifumi Hashimoto
  • Patent number: 11359636
    Abstract: A vacuum pump comprises: a rotor; a stator; a rolling bearing configured to support a rotor shaft provided at the rotor; and a vibration sensor configured to detect vibration of the rolling bearing.
    Type: Grant
    Filed: May 2, 2019
    Date of Patent: June 14, 2022
    Assignee: Shimadzu Corporation
    Inventors: Toshifumi Hashimoto, Nobuhiko Moriyama
  • Publication number: 20220090311
    Abstract: The present disclosure relates to a clothes dryer. The clothes dryer includes a drum configured to accommodate and dry clothes, and a lint removal device configured to remove lint in air flowing out of the drum. The lint removal device includes a filter part configured such that the lint is adhered thereto, and a screw rotatably disposed at an inner side of the filter part to push out the lint adhered to the filter part. The screw includes a shaft, and a blade extending from the shaft and having a helical shape, and the blade has elasticity to remove foreign substances introduced into the lint removal device without damage to the filter part.
    Type: Application
    Filed: November 22, 2019
    Publication date: March 24, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hitoshi MINAI, Toshifumi HASHIMOTO, Shigenori HATO, Ryo AOKI
  • Publication number: 20220084586
    Abstract: A semiconductor memory device includes a plurality of memory cells, a word line connected to gates of the memory cells, a bit line electrically connected to one ends of the memory cells through a plurality of select gate transistors, respectively, the select gate transistors including two outer select gate transistors and one or more inner select gate transistors between the two outer select gate transistors, two outer select gate lines connected to gates of the two outer select gate transistors, respectively, one or more inner select gate lines connected to gates of the one or more inner select gate transistors, respectively, and a voltage generation circuit configured to independently control supply of voltages to the outer select gate lines and the inner select gate lines during an operation to read data stored in the memory cells.
    Type: Application
    Filed: February 25, 2021
    Publication date: March 17, 2022
    Inventors: Tomoki NAKAGAWA, Koji KATO, Toshifumi HASHIMOTO
  • Publication number: 20220052071
    Abstract: A semiconductor memory device includes a substrate, a plurality of first conductive layers, a second conductive layer disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers, a first semiconductor column, a first electric charge accumulating film, a first wiring disposed at a position farther from or a position closer to the substrate than the plurality of first conductive layers and the second conductive layer, a first contact that is disposed between one end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring, and a second contact that is disposed between another end of the second conductive layer and the first semiconductor column and is electrically connected to the second conductive layer and the first wiring.
    Type: Application
    Filed: February 22, 2021
    Publication date: February 17, 2022
    Applicant: Kioxia Corporation
    Inventor: Toshifumi HASHIMOTO
  • Publication number: 20210343644
    Abstract: A semiconductor memory device includes a semiconductor substrate, memory blocks, a first wiring, a second wiring, a first contact, a first transistor, and a second transistor. The memory blocks are spaced from the semiconductor substrate in a first direction and are arranged in a second direction. The first wiring is farther from the semiconductor substrate than the memory blocks. The second wiring is closer to the semiconductor substrate than the memory blocks. The first contact is electrically connected between the first wiring and the second wiring. The first and second transistors are disposed on the semiconductor substrate. The first transistor is electrically connected between the second wiring and a first memory block. The second transistor is electrically connected between the second wiring and a second memory block. The first contact is disposed between the first transistor and the second transistor in the second direction.
    Type: Application
    Filed: January 27, 2021
    Publication date: November 4, 2021
    Applicant: Kioxia Corporation
    Inventors: Toshifumi HASHIMOTO, Jumpei SATO
  • Patent number: 11118304
    Abstract: A clothes dryer comprises a drum to stir clothes accommodated therein, an exhaust duct configured to discharge air inside the drum, a lint removing device including a filter to remove lint in air discharged to the exhaust duct, and a foreign-substance separating plate installed between the exhaust duct and the lint removing device to separate solid foreign substances in the air discharged to the exhaust duct.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: September 14, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenori Hato, Toshifumi Hashimoto, Yuji Aoshima, Hitoshi Minai
  • Patent number: 11017837
    Abstract: According to one embodiment, a memory system includes: a semiconductor memory including a memory cell array, the memory cell array including a memory cell, and a controller configured to issue a first read command sequence after a lapse of a first time period from access to the semiconductor memory, and issue a second read command sequence after a lapse of a second time period from access to the semiconductor memory. When the controller issues the first read command sequence, the semiconductor memory applies a first voltage and a second voltage to the memory cell. When the controller issues the second read command sequence, the semiconductor memory applies a third voltage and a fourth voltage to the memory cell.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: May 25, 2021
    Assignee: KIOXIA CORPORATION
    Inventor: Toshifumi Hashimoto
  • Publication number: 20210065771
    Abstract: According to one embodiment, a memory system includes: a semiconductor memory including a memory cell array, the memory cell array including a memory cell, and a controller configured to issue a first read command sequence after a lapse of a first time period from access to the semiconductor memory, and issue a second read command sequence after a lapse of a second time period from access to the semiconductor memory. When the controller issues the first read command sequence, the semiconductor memory applies a first voltage and a second voltage to the memory cell. When the controller issues the second read command sequence, the semiconductor memory applies a third voltage and a fourth voltage to the memory cell.
    Type: Application
    Filed: March 9, 2020
    Publication date: March 4, 2021
    Applicant: KIOXIA CORPORATION
    Inventor: Toshifumi HASHIMOTO
  • Patent number: 10937502
    Abstract: A semiconductor memory device includes a first memory transistor, a first wiring connected to a gate electrode of the first memory transistor, a connection transistor connected to the first wiring, and a second wiring connected to the connection transistor. In a first write operation for the first memory transistor, during a first time period, a voltage of the first wiring increases to a first voltage and a voltage of the second wiring increases to a second voltage larger than the first voltage, and during a second time period directly after the first time period and directly after the connection transistor is turned ON, the voltage of the first wiring increases to a third voltage larger than the first voltage and smaller than the second voltage, and the voltage of the second wiring decreases to a fourth voltage larger than the first voltage and smaller than the second voltage.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: March 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Toshifumi Hashimoto