Abstract: A vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor substrate, a first conductive layer formed in a predetermined region including a side wall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.

Abstract: A vertical metal oxide semiconductor field effect transistor has a trench substantially vertically formed in a major surface of a semiconductor substrate, a first conductive layer formed in a predetermined region including a side wall surface of the trench on a gate insulating film, lower and upper diffusion layers formed in the bottom of the trench and a surface layer of the semiconductor substrate, preferably a channel doped region formed in the semiconductor substrate between the upper and lower diffusion layers, and a second conductive layer formed in contact with the lower diffusion layer in the bottom of the trench and insulated from the first conductive layer so as to fill the trench. The first conductive layer serves as a gate electrode, and the diffusion layers serves as source/drain regions, respectively. A method of manufacturing the vertical MOSFET is also proposed.

Abstract: A semiconductor device has memory cells respectively located at intersections of bit and word lines arranged in a matrix form, each of the memory cells being constituted by a single insulated gate transistor and a single capacitor. One memory cell is formed in an element formation region defined by each of trenches arranged in a matrix form. The capacitor has an insulating film formed along part of a side wall surface of a trench formed in at least a direction of thickness of a semiconductor substrate and a conductive layer formed along the insulating film. The transistor has a gate insulating film adjacent to the capacitor and formed along a remaining portion of the side wall surface of the trench, a gate electrode formed along the gate insulating film, and a diffusion region formed in a major surface of the semiconductor substrate which is adjacent to the gate insulating film.

Abstract: A read-only memory has memory cells each with a vertical metal oxide semiconductor field effect transistor and a bit line. The vertical metal oxide semiconductor field effect transistor has a gate electrode serving as a word line, a source, a drain, and a vertical channel region between the source and drain constituted by first and second diffusion layers. The gate electrode is formed on a side wall of a trench, which has a pair of side walls substantially perpendicular to a major surface of a semiconductor substrate of a first conductivity type and an interconnecting bottom surface substantially perpendicular to the side wall surfaces. The first and second diffusion layers of a second conductivity type are formed in an upper portion of the semiconductor substrate and in a bottom of the trench, respectively. The bit lines are formed in a predetermined pattern.