Patents by Inventor Toshifumi Takeda
Toshifumi Takeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7199432Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: August 26, 2004Date of Patent: April 3, 2007Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 7187039Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: April 8, 2005Date of Patent: March 6, 2007Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 7163870Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: September 29, 2004Date of Patent: January 16, 2007Assignee: Renesas Technology Corp.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 7002830Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: GrantFiled: October 28, 2003Date of Patent: February 21, 2006Assignees: Renesas Technology Corp., Hitachi VLSI Engineering Corp.Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
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Publication number: 20060018172Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: ApplicationFiled: September 19, 2005Publication date: January 26, 2006Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
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Patent number: 6982465Abstract: The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics. In a semiconductor device including an n-channel field effect transistor 10 and a p-channel field effect transistor 30, a stress control film 19 covering a gate electrode 15 of the n-channel field effect transistor 10 undergoes film stress mainly composed of tensile stress. A stress control film 39 covering a gate electrode 15 of the p-channel field effect transistor 30 undergoes film stress mainly caused by compression stress compared to the film 19 of the n-channel field effect transistor 10. Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.Type: GrantFiled: December 6, 2001Date of Patent: January 3, 2006Assignee: Renesas Technology Corp.Inventors: Yukihiro Kumagai, Hiroyuki Ohta, Fumio Ootsuka, Shuji Ikeda, Takahiro Onai, Hideo Miura, Katsuhiko Ichinose, Toshifumi Takeda
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Publication number: 20050179110Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: April 8, 2005Publication date: August 18, 2005Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20050121727Abstract: The object of the present invention is to provide a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor, which has a high degree of reliability and excellent drain current characteristics. The gist of the invention for attaining the object resides in disposing a silicon nitride film to the side wall of a trench for an active region in which the n-type channel field effect transistor is formed and disposing the silicon nitride film only in the direction perpendicular to the channel direction to the sidewall of the trench for the active region of the p-type channel field effect transistor. According to the present invention, a semiconductor device comprising an n-type channel field effect transistor and a p-type channel field effect transistor of excellent current characteristics can be provided.Type: ApplicationFiled: November 11, 2002Publication date: June 9, 2005Inventors: Norio Ishitsuka, Yukihiro Kumagai, Hideo Miura, Shuji Ikeda, Toshifumi Takeda, Hiroyuki Ohta
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Publication number: 20050040538Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: October 4, 2004Publication date: February 24, 2005Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20050040537Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: September 29, 2004Publication date: February 24, 2005Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20050026405Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: August 26, 2004Publication date: February 3, 2005Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 6751138Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: GrantFiled: November 21, 2002Date of Patent: June 15, 2004Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
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Publication number: 20040090838Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: ApplicationFiled: October 28, 2003Publication date: May 13, 2004Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
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Publication number: 20040075148Abstract: The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics.Type: ApplicationFiled: June 6, 2003Publication date: April 22, 2004Inventors: Yukihiro Kumagai, Hiroyuki Ohta, Fumio Ootsuka, Shuji Ikeda, Takahiro Onai, Hideo Miura, Katsuhiko Ichinose, Toshifumi Takeda
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Publication number: 20040012093Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: July 14, 2003Publication date: January 22, 2004Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Patent number: 6664642Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: February 15, 2002Date of Patent: December 16, 2003Assignee: Hitachi, Ltd.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20030095434Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: ApplicationFiled: November 21, 2002Publication date: May 22, 2003Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
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Patent number: 6501689Abstract: A nonvolatile storage element of a single-layer gate type structure is arranged so that a floating gate is formed of a conductive layer which partly overlaps with a control gate, formed of a diffused layer, and is provided with a barrier layer covering a part of or the whole surface of the floating gate. Nonvolatile storage elements characterized as such are used for redundancy control of defects or change of functions.Type: GrantFiled: October 25, 2001Date of Patent: December 31, 2002Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Kenichi Kuroda, Toshifumi Takeda, Hisahiro Moriuchi, Masaki Shirai, Jiroh Sakaguchi, Akinori Matsuo, Shoji Yoshida
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Patent number: 6433438Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: GrantFiled: May 2, 2001Date of Patent: August 13, 2002Assignee: Hitachi, Ltd.Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda
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Publication number: 20020074611Abstract: Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.Type: ApplicationFiled: February 15, 2002Publication date: June 20, 2002Inventors: Yasushi Koubuchi, Koichi Nagasawa, Masahiro Moniwa, Youhei Yamada, Toshifumi Takeda