Patents by Inventor Toshiharu Tanaka

Toshiharu Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200255312
    Abstract: A wash water processing method and a wash water processing apparatus in a simple structure capable of effectively decomposing organic matters and killing bacteria contained in wash water, extending the life of a filter of a filtration apparatus and an ion-exchange resin and, furthermore, extending a bacteria-killing/washing interval of a washing processing part. In the wash water processing apparatus (11) and the washing method, a wash water accommodation part (12) into which processed water processed in a washing processing part (10) flows and a filtration mechanism part (14) are connected and the wash water accommodation part has connected in a circulatable manner thereto an inflow flow path and an outflow flow path of a sterilization and purification unit which organically couples respective functions of an ozone supply part which supplies ozone, an ultraviolet irradiation part which irradiates with ultraviolet rays, and a photocatalysis part which causes a photocatalyst to act.
    Type: Application
    Filed: October 29, 2018
    Publication date: August 13, 2020
    Inventors: Katsuhisa YATA, Takako SAKURAI, Satoshi ITO, Toshiharu TANAKA
  • Patent number: 10466204
    Abstract: A welding state inspection method for ultrasonic-welded plate-like members includes the steps of measuring energy that has been transmitted to an anvil when ultrasonic-welding a plurality of plate-like members stacked on the anvil while pressing a horn that vibrates against the plate-like members; and determining a quality of a welding state of the plate-like members on the basis of the energy measured in the measuring step.
    Type: Grant
    Filed: December 25, 2013
    Date of Patent: November 5, 2019
    Assignees: Automotive Energy Supply Corporation, Envision AESC Japan Ltd.
    Inventors: Koichi Kawamoto, Shuji Yoshida, Yutaka Suzuki, Takashi Matsuoka, Toshiharu Tanaka
  • Patent number: 10211259
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate extending in a first direction and a second direction, the first and second directions intersecting each other; a first wiring line disposed above the semiconductor substrate and extending in the first direction; a second wiring line disposed above the semiconductor substrate and extending in a third direction, the third direction intersecting the first direction and the second direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a first insulating film disposed aligned with the second wiring line in the first direction; a first film disposed between the first wiring line and the first insulating film; and a second film disposed between the first insulating film and the first film and configured from a material different from that of the first film.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: February 19, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi Oga, Mutsumi Okajima, Natsuki Fukuda, Takeshi Yamaguchi, Toshiharu Tanaka, Hiroyuki Ode
  • Patent number: 10192928
    Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.
    Type: Grant
    Filed: September 15, 2017
    Date of Patent: January 29, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Natsuki Fukuda, Mutsumi Okajima, Atsushi Oga, Toshiharu Tanaka, Takeshi Yamaguchi, Takeshi Takagi, Masanori Komura
  • Patent number: 10074694
    Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction and a resistance change film provided between the first wiring and the second wiring. The second wiring includes a first conductive layer and a first intermediate layer including a first region provided between the first conductive layer and the resistance change film. The first intermediate layer includes a material having nonlinear resistance characteristics.
    Type: Grant
    Filed: February 8, 2016
    Date of Patent: September 11, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Takagi, Takeshi Yamaguchi, Masaki Yamato, Hiroyuki Ode, Toshiharu Tanaka
  • Patent number: 9924325
    Abstract: There is provided an information processing system including an acquisition section configured to acquire a movement direction and a movement purpose from each one of a plurality of terminal devices; and a guide information issuing section configured to issue a guide information which is generate based on the movement direction and the movement purpose of the a plurality of terminal devices.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: March 20, 2018
    Assignee: SONY CORPORATION
    Inventor: Toshiharu Tanaka
  • Patent number: 9905759
    Abstract: According to one embodiment, a memory device includes a pillar, a first wiring, a second wiring, an insulating film provided between the first wiring and the second wiring, a first layer provided between the first wiring and the pillar in the second direction and including a first metal oxide containing a first metal and oxygen, a second layer provided between the second wiring and the pillar in the second direction and including the first metal oxide containing the first metal and oxygen, and an intermediate film provided between the pillar and the first layer and between the pillar and the second layer in the second direction and including a second metal oxide containing the first metal and oxygen. Concentration of oxygen contained in the first metal oxide is lower than concentration of oxygen contained in the second metal oxide.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: February 27, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takeshi Takagi, Takeshi Yamaguchi, Masaki Yamato, Hiroyuki Ode, Toshiharu Tanaka
  • Publication number: 20180006089
    Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 4, 2018
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Natsuki FUKUDA, Mutsumi OKAJIMA, Atsushi OGA, Toshiharu TANAKA, Takeshi YAMAGUCHI, Takeshi TAKAGI, Masanori KOMURA
  • Publication number: 20170373119
    Abstract: A semiconductor memory device according to an embodiment comprises: a semiconductor substrate extending in a first direction and a second direction, the first and second directions intersecting each other; a first wiring line disposed above the semiconductor substrate and extending in the first direction; a second wiring line disposed above the semiconductor substrate and extending in a third direction, the third direction intersecting the first direction and the second direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a first insulating film disposed aligned with the second wiring line in the first direction; a first film disposed between the first wiring line and the first insulating film; and a second film disposed between the first insulating film and the first film and configured from a material different from that of the first film.
    Type: Application
    Filed: March 21, 2017
    Publication date: December 28, 2017
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Atsushi OGA, Mutsumi OKAJIMA, Natsuki FUKUDA, Takeshi YAMAGUCHI, Toshiharu TANAKA, Hiroyuki ODE
  • Patent number: 9768233
    Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body facing the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first conductive films.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: September 19, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Natsuki Fukuda, Mutsumi Okajima, Atsushi Oga, Toshiharu Tanaka, Takeshi Yamaguchi, Takeshi Takagi, Masanori Komura
  • Publication number: 20170256588
    Abstract: A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film; a first conductive body facing the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first conductive films.
    Type: Application
    Filed: March 18, 2016
    Publication date: September 7, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Natsuki FUKUDA, Mutsumi OKAJIMA, Atsushi OGA, Toshiharu TANAKA, Takeshi YAMAGUCHI, Takeshi TAKAGI, Masanori KOMURA
  • Patent number: 9721961
    Abstract: In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: August 1, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mutsumi Okajima, Atsushi Oga, Takeshi Yamaguchi, Hiroyuki Ode, Toshiharu Tanaka, Natsuki Fukuda
  • Patent number: 9704922
    Abstract: According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: July 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi Oga, Mutsumi Okajima, Takeshi Yamaguchi, Hiroyuki Ode, Toshiharu Tanaka, Natsuki Fukuda
  • Publication number: 20170117039
    Abstract: According to an embodiment, a nonvolatile semiconductor memory device comprises: a memory cell array; and a control circuit that manages a setting operation and a read operation. The memory cell array comprises: a first wiring line; a second wiring line intersecting the first wiring line; and a memory cell including a variable resistance element and a nonlinear element. The variable resistance element is configured having a first metal film, a first variable resistance film, a second variable resistance film, and a second metal film stacked and disposed therein in this order. A work function of the second metal film is smaller than a work function of the first metal film.
    Type: Application
    Filed: March 15, 2016
    Publication date: April 27, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Masaki YAMATO, Takeshi YAMAGUCHI, Takeshi TAKAGI, Hiroyuki ODE, Toshiharu TANAKA
  • Publication number: 20170062713
    Abstract: According to one embodiment, A memory device includes a pillar, a first wiring, a second wiring, an insulating film provided between the first wiring and the second wiring, a first layer provided between the first wiring and the pillar in the second direction and including a first metal oxide containing a first metal and oxygen, a second layer provided between the second wiring and the pillar in the second direction and including the first metal oxide containing the first metal and oxygen, and an intermediate film provided between the pillar and the first layer and between the pillar and the second layer in the second direction and including a second metal oxide containing the first metal and oxygen. Concentration of oxygen contained in the first metal oxide is lower than concentration of oxygen contained in the second metal oxide.
    Type: Application
    Filed: February 2, 2016
    Publication date: March 2, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi TAKAGI, Takeshi YAMAGUCHI, Masaki YAMATO, Hiroyuki ODE, Toshiharu TANAKA
  • Patent number: 9559300
    Abstract: In accordance with an embodiment, a resistive random access memory device includes a substrate, first and second wiring lines, and a storage cell. The first and second wiring lines are disposed on the substrate so as to intersect each other. The storage cell is disposed between the first and second wiring lines at the intersection of the first and second wiring lines and includes a first electrode, a resistive switching film on the first electrode, a second electrode on the resistive switching film, and a tantalum oxide (TaOx) layer. The first electrode is electrically connected to the first wiring line. The second electrode is electrically connected to the second wiring line. The tantalum oxide (TaOx) layer is disposed between the first electrode and the resistive switching film and is in contact with the resistive switching film.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: January 31, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki Ode, Takeshi Yamaguchi, Takeshi Takagi, Toshiharu Tanaka, Masaki Yamato
  • Publication number: 20170025475
    Abstract: According to one embodiment, a memory device includes a first wiring extending in a first direction, a second wiring extending in a second direction crossing the first direction and a resistance change film provided between the first wiring and the second wiring. The second wiring includes a first conductive layer and a first intermediate layer including a first region provided between the first conductive layer and the resistance change film. The first intermediate layer includes a material having nonlinear resistance characteristics.
    Type: Application
    Filed: February 8, 2016
    Publication date: January 26, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Takeshi TAKAGI, Takeshi YAMAGUCHI, Masaki YAMATO, Hiroyuki ODE, Toshiharu TANAKA
  • Patent number: 9543002
    Abstract: The transistor layer is disposed above or below the memory layer and includes a transistor. The wiring line layer connects the memory layer and the transistor layer. The memory cell array comprises a plurality of select gate lines connected to gates of a plurality of the select transistors aligned in a third direction. The wiring line layer comprises: a first connecting wiring line connected to a first select gate line of the plurality of select gate lines and extending in the third direction; and a second connecting wiring line connected to a second select gate line adjacent in a second direction to the first select gate line. This second connecting wiring line at least comprises: a first portion extending in the third direction; and a second portion extending from the first portion to a layer below the first connecting wiring line.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: January 10, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Toshiharu Tanaka
  • Publication number: 20160351628
    Abstract: In this semiconductor memory device, the first conducting layers are arrayed laminated in a first direction, and extend in a second direction intersecting with the first direction. The first conducting layers are arrayed in a third direction via interlayer insulating films. The third direction intersects with the first direction and the second direction. The interlayer insulating film is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer is disposed between the first conducting layers arrayed in the third direction, and extends in the first direction. The second conducting layer has an approximately circular cross-sectional shape intersecting with the first direction. The variable resistance layer surrounds a peripheral area of the second conducting layer, and is disposed at a position between the second conducting layer and the first conducting layer.
    Type: Application
    Filed: December 15, 2015
    Publication date: December 1, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mutsumi OKAJIMA, Atsushi OGA, Takeshi YAMAGUCHI, Hiroyuki ODE, Toshiharu TANAKA, Natsuki FUKUDA
  • Publication number: 20160351624
    Abstract: According to one embodiment, this semiconductor memory device includes first conducting layers, a memory layer, and second conducting layers. The first conducting layers are laminated at predetermined pitches in a first direction perpendicular to a substrate. The first conducting layers extend in a second direction parallel to the substrate. The second conducting layer extends in the first direction. A memory layer surrounds a circumference of the second conductive layer. The first conductive layers is in contact with a side surface of the second conductive layer via the memory layer. The memory cells are provided at intersections of the first conducting layers and the second conducting layer.
    Type: Application
    Filed: September 10, 2015
    Publication date: December 1, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Atsushi OGA, Mutsumi OKAJIMA, Takeshi YAMAGUCHI, Hiroyuki ODE, Toshiharu TANAKA, Natsuki FUKUDA