Patents by Inventor Toshihide Nabatame

Toshihide Nabatame has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7790627
    Abstract: A method of manufacturing a metal compound thin film is disclosed. The method may include forming a first metal compound layer on a substrate by atomic layer deposition, performing annealing on the first metal compound layer in an atmosphere containing a nitrogen compound gas, thereby diffusing nitrogen into the first metal compound layer, and forming a second metal compound layer on the first metal compound layer by atomic layer deposition.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: September 7, 2010
    Assignee: Rohm Co., Ltd.
    Inventors: Kunihiko Iwamoto, Toshihide Nabatame, Koji Tominaga, Tetsuji Yasuda
  • Patent number: 7772678
    Abstract: After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film Annealing is done in an NH3 atmosphere so as to diffuse nitrogen in the metal oxide film. Building of the metal oxide film and diffusion of nitrogen are repeated several times, whereupon annealing is done in an O2 atmosphere. By annealing the film in an O2 atmosphere at a temperature higher than 650° C., the leak current in the metal oxide film is controlled.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: August 10, 2010
    Assignees: Rohm Co., Ltd., Horiba, Ltd., Renesas Technology Corp.
    Inventors: Kunihiko Iwamoto, Koji Tominaga, Toshihide Nabatame, Tomoaki Nishimura
  • Publication number: 20100187644
    Abstract: The transistor characteristics of a MIS transistor provided with a gate insulating film formed to contain oxide with a relative dielectric constant higher than that of silicon oxide are improved. After a high dielectric layer made of hafnium oxide is formed on a main surface of a semiconductor substrate, the main surface of the semiconductor substrate is heat-treated in a non-oxidation atmosphere. Next, an oxygen supplying layer made of hafnium oxide deposited by ALD and having a thickness smaller than that of the high dielectric layer is formed on the high dielectric layer, and a cap layer made of tantalum nitride is formed. Thereafter, the main surface of the semiconductor substrate is heat-treated.
    Type: Application
    Filed: April 1, 2010
    Publication date: July 29, 2010
    Inventor: Toshihide NABATAME
  • Patent number: 7618855
    Abstract: A technology capable of improving the yield in a manufacturing process of a MISFET with a gate electrode formed of a metal silicide film. A gate insulating film is formed on a semiconductor substrate and silicon gate electrodes formed of a polysilicon film are formed on the gate insulating film. Then, after a silicon oxide film is formed so as to cover the silicon gate electrodes, a surface of the silicon oxide film is polished by CMP, thereby exposing the surface of the silicon gate electrodes. Subsequently, a patterned insulating film is formed on the silicon oxide film. Thereafter, an adhesion film is formed on the silicon oxide film and the insulating film. Then, a nickel film is formed on the adhesion film. Thereafter, a silicide reaction is caused to occur between the silicon gate electrode and the nickel film via the adhesion film.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: November 17, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Masaru Kadoshima, Toshihide Nabatame
  • Patent number: 7586755
    Abstract: Through an improvement of module size increase due to mounting a single passive element on a substrate and an increase in the mounting cost, to provide a highly reliable, high performance and small sized electronic circuit component which permits to integrate a variety of electronic parts such as capacitors, inductors and resistors in a high density with low cost. The electronic circuit component comprises an insulator substrate, a plurality of electrodes having different areas provided on the insulator substrate, one or more elements selected from a capacitor element of dielectric material sandwiched between the electrodes, an inductor element and resistor element, a metal wiring connecting the elements, a metal terminal part of a part of the metal wiring and an organic insulator material covering the elements and the circumference of the metal wiring portion excluding the metal terminal portion.
    Type: Grant
    Filed: August 6, 2007
    Date of Patent: September 8, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Toshiya Satoh, Masahiko Ogino, Takao Miwa, Takashi Naitou, Takashi Namekawa, Toshihide Nabatame, Shigehisa Motowaki
  • Publication number: 20090146216
    Abstract: After forming a pure silicon oxide film on respective surfaces of an n-type well and a p-type well, an oxygen deficiency adjustment layer made of an oxide of 2A group elements, an oxide of 3A group elements, an oxide of 3B group elements, an oxide of 4A group elements, an oxide of 5A group elements or the like, a high dielectric constant film, and a conductive film having a reduction catalyst effect to hydrogen are sequentially deposited on the silicon oxide film, and the substrate is heat treated in the atmosphere containing H2, thereby forming a dipole between the oxygen deficiency adjustment layer and the silicon oxide film. Then, the conductive film, the high dielectric constant film, the oxygen deficiency adjustment layer, the silicon oxide film and the like are patterned, thereby forming a gate electrode and a gate insulating film.
    Type: Application
    Filed: December 6, 2008
    Publication date: June 11, 2009
    Inventors: Toshihide NABATAME, Kunihiko IWAMOTO, Yuuichi KAMIMUTA
  • Publication number: 20090096067
    Abstract: After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film. Annealing is done in an NH3 atmosphere so as to diffuse nitrogen in the metal oxide film. Building of the metal oxide film and diffusion of nitrogen are repeated several times, whereupon annealing is done in an O2 atmosphere. By annealing the film in an O2 atmosphere at a temperature higher than 650° C., the leak current in the metal oxide film is controlled.
    Type: Application
    Filed: December 12, 2008
    Publication date: April 16, 2009
    Applicants: ROHM CO., LTD., HORIBA, LTD., RENESAS TECHNOLOGY CORP.,
    Inventors: Kunihiko IWAMOTO, Koji TOMINAGA, Toshihide NABATAME, Tomoaki NISHIMURA
  • Patent number: 7511338
    Abstract: An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.
    Type: Grant
    Filed: September 6, 2006
    Date of Patent: March 31, 2009
    Assignees: Renesas Technology Corp., Tokyo Electron Limited
    Inventors: Toshihide Nabatame, Masaru Kadoshima, Hiroyuki Takaba
  • Patent number: 7482234
    Abstract: After the surface of the substrate is cleaned, an interface layer or an antidiffusion film is formed. A metal oxide film is built upon the antidiffusion film Annealing is done in an NH3 atmosphere so as to diffuse nitrogen in the metal oxide film. Building of the metal oxide film and diffusion of nitrogen are repeated several times, whereupon annealing is done in an O2 atmosphere. By annealing the film in an O2 atmosphere at a temperature higher than 650° C., the leak current in the metal oxide film is controlled.
    Type: Grant
    Filed: August 27, 2004
    Date of Patent: January 27, 2009
    Assignees: Rohm Co., Ltd., Horiba, Ltd., Renesas Technology Corp.
    Inventors: Kunihiko Iwamoto, Koji Tominaga, Toshihide Nabatame, Tomoaki Nishimura
  • Publication number: 20090011608
    Abstract: The transistor characteristics of a MIS transistor provided with a gate insulating film formed to contain oxide with a relative dielectric constant higher than that of silicon oxide are improved. After a high dielectric layer made of hafnium oxide is formed on a main surface of a semiconductor substrate, the main surface of the semiconductor substrate is heat-treated in a non-oxidation atmosphere. Next, an oxygen supplying layer made of hafnium oxide deposited by ALD and having a thickness smaller than that of the high dielectric layer is formed on the high dielectric layer, and a cap layer made of tantalum nitride is formed. Thereafter, the main surface of the semiconductor substrate is heat-treated.
    Type: Application
    Filed: May 7, 2008
    Publication date: January 8, 2009
    Inventor: Toshihide NABATAME
  • Publication number: 20080293229
    Abstract: An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.
    Type: Application
    Filed: July 30, 2008
    Publication date: November 27, 2008
    Inventors: Toshihide Nabatame, Masaru Kadoshima, Hiroyuki Takaba
  • Publication number: 20080283929
    Abstract: In a p channel MOS transistor and an n channel MOS transistor each having a gate electrode made of metal on a gate insulating film made of oxide whose relative dielectric constant is higher than that of silicon oxide, threshold voltage thereof is reduced. A gate insulating film of a p channel MOS transistor and an n channel MOS transistor is made of hafnium oxide, a gate electrode of the p channel MOS transistor is made of ruthenium, and a gate electrode of the n channel MOS transistor is made of alloy containing ruthenium as a base material and hafnium.
    Type: Application
    Filed: May 11, 2008
    Publication date: November 20, 2008
    Inventor: Toshihide Nabatame
  • Patent number: 7419920
    Abstract: A metal oxide thin film may be obtained by providing a source gas and an oxidizer gas. The source gas may include a hydrolyzable metallic compound. The oxidizer gas may include a hydrate of a metal salt. The metal oxide thin film may be obtained by alternately feeding the source gas and the oxidizer gas into a reaction chamber in which a substrate is placed.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: September 2, 2008
    Assignees: HORIBA, Ltd., Rohm Co., Ltd., Renesas Technology Corp.
    Inventors: Koji Tominaga, Kunihiko Iwamoto, Toshihide Nabatame
  • Publication number: 20080174976
    Abstract: Through an improvement of module size increase due to mounting a single passive element on a substrate and an increase in the mounting cost, to provide a highly reliable, high performance and small sized electronic circuit component which permits to integrate a variety of electronic parts such as capacitors, inductors and resistors in a high density with low cost. The electronic circuit component comprises an insulator substrate, a plurality of electrodes having different areas provided on the insulator substrate, one or more elements selected from a capacitor element of dielectric material sandwiched between the electrodes, an inductor element and resistor element, a metal wiring connecting the elements, a metal terminal part of a part of the metal wiring and an organic insulator material covering the elements and the circumference of the metal wiring portion excluding the metal terminal portion.
    Type: Application
    Filed: August 6, 2007
    Publication date: July 24, 2008
    Applicant: HITACHI, LTD.
    Inventors: Toshiya SATOH, Masahiko OGINO, Takao MIWA, Takashi NAITOU, Takashi NAMEKAWA, Toshihide NABATAME, Shigehisa MOTOWAKI
  • Publication number: 20080166867
    Abstract: A method of manufacturing a metal compound thin film is disclosed. The method may include forming a first metal compound layer on a substrate by atomic layer deposition, performing annealing on the first metal compound layer in an atmosphere containing a nitrogen compound gas, thereby diffusing nitrogen into the first metal compound layer, and forming a second metal compound layer on the first metal compound layer by atomic layer deposition.
    Type: Application
    Filed: December 11, 2007
    Publication date: July 10, 2008
    Applicants: ROHM CO., LTD., Horiba, Ltd., Renesas Technology Corp., National Institute of Advanced Industrial Science and Technology
    Inventors: Kunihiko Iwamoto, Toshihide Nabatame, Koji Tominaga, Tetsuji Yasuda
  • Patent number: 7397094
    Abstract: To provide a semiconductor device that enables to suppress a defect density of a gate insulating film of an MISFET, gain a sufficient electric characteristic thereof, and make an Equivalent Oxide Thickness (EOT) of the gate insulating film 1.0 nm or less. The MISFETs are formed to have the gate insulating film formed on a main surface of a silicon substrate, and a gate electrode formed on the gate insulating film, wherein the gate insulating film includes a metal silicate layer formed by a metal oxide layer and a silicon oxide layer and the metal silicate layer is formed so as to have concentration gradients of metal and silicon from a silicon substrate side toward a gate electrode side.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: July 8, 2008
    Assignees: Renesas Technology Corporation, National Institute of Advanced Industrial Science and Technology, Rohm Co., Ltd., Horiba., Ltd.
    Inventors: Toshihide Nabatame, Akira Toriumi, Tsuyoshi Horikawa, Kunihiko Iwamoto, Koji Tominaga
  • Patent number: 7387686
    Abstract: A metal atomic layer and an oxygen atomic layer are formed in this order by ALD, followed by rapid heating through RTA (Rapid Thermal Annealing). This cycle of steps is repeated to form a high dielectric constant film.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: June 17, 2008
    Assignee: Rohm Co., Ltd.
    Inventors: Kunihiko Iwamoto, Toshihide Nabatame, Koji Tominaga, Tetsuji Yasuda
  • Patent number: 7372112
    Abstract: A high dielectric gate insulating film having the structure that a high-nitrogen layer, a low-nitrogen layer, and a high-nitrogen layer are layered in this order from a silicon-substrate side.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: May 13, 2008
    Assignees: Rohm Co., Ltd., Renesas Technology Corp., Horiba, Ltd.
    Inventors: Kunihiko Iwamoto, Toshihide Nabatame, Koji Tominaga, Tetsuji Yasuda
  • Publication number: 20080026148
    Abstract: A throughput during a process of forming a thin film is improved and a thin film of high quality is produced at low cost. For this purpose, a film forming system comprises a chamber 8, a precursory gas supplying line 2 to supply the chamber 8 with precursory gas, a reactive gas supplying line 1 to supply the chamber 8 with reactive gas, and a purge gas supplying line 3 to supply purge gas that purges the precursory gas and the reactive gas, and forms a thin film on a substrate 82 in the chamber 8 by supplying the precursory gas or the reactive gas and purging alternately, and further comprises a middle line 22 having a certain volume that is arranged on a part or all of the precursor supplying line 2 and into which the precursory gas can be filled at a time when the precursory gas is not supplied, and/or a middle line 12 having a certain volume that is arranged on a part or all of the reactive gas supplying line 1 and into which the reactive gas can be filled at a time when the reactive gas is not supplied.
    Type: Application
    Filed: December 22, 2004
    Publication date: January 31, 2008
    Inventors: Koji Tominaga, Tetsuji Yasuda, Toshihide Nabatame, Kunihiko Iwamoto
  • Patent number: 7323381
    Abstract: A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of an n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide (HfO2) film. Also, the gate electrode of the n channel MIS transistor is composed of an Ni (nickel) silicide film, and the gate electrode of the p channel MIS transistor is composed of a Pt (platinum) film. In this structure, Fermi level pinning of the gate electrodes can be prevented. Therefore, the increase of the threshold voltage of the n channel MIS transistor and the p channel MIS transistor can be inhibited.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: January 29, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Masaru Kadoshima, Toshihide Nabatame