Abstract: A thin film capacitor comprising a lower electrode formed on a predetermined surface, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, wherein the end portion of the lower electrode is further covered by an insulator other than the dielectric layer.

Abstract: A semiconductor device is provided with a first MISFET including a first gate insulating film including a HfAlO film formed over a semiconductor substrate and a first gate electrode, including a nickel silicide film, formed over the first gate insulating film. An aluminum concentration of the HfAlO film on a side of the HfAlO film facing the first gate electrode is higher than an aluminum concentration of the HfAlO film on a side of the HfAlO film facing the semiconductor substrate.

Abstract: In a manufacturing process of a semiconductor device having a CMISFET, first, a silicon film and a first metal film made of a first metal are reacted with each other through heat treatment, thereby forming a gate electrode of a p-channel type MISFET and a dummy gate electrode of an n-channel type MISFET, which are formed of metal silicide. Subsequently, an insulating film is formed so as to cover the gate electrode but expose the dummy electrode, and then, a metal film formed of a second metal having a work function lower than that of the first metal. The metal film contacts with the dummy gate but not with the gate electrode due to the insulating film interposing therebetween. Thereafter, through heat treatment, the dummy gate electrode and the metal film are reacted with each other to form a gate electrode of the n-channel type MISFET.

Abstract: A method of manufacturing an MIS semiconductor device includes forming a high dielectric film as a gate insulator on a semiconductor substrate of a first conductivity type, heat-treating the semiconductor substrate in ambient with hydrogen and oxygen gases to form an interface layer between the semiconductor substrate and the high dielectric film, forming a conductive film on the high dielectric film after the interfacial layer is formed, processing the conductive film in a gate pattern to form a gate electrode, and doping the semiconductor substrate with impurities of a second conductivity type using the gate electrode as a mask to form source/drain regions.

Abstract: A method of manufacturing an MIS semiconductor device includes forming a high dielectric film on a main surface of a semiconductor substrate, forming a silicon film on the high dielectric film, annealing the semiconductor substrate after the silicon film is formed, processing the high dielectric film and the silicon film into a gate pattern after the semiconductor substrate is annealed, to form a gate insulating film and a gate electrode, and forming source and drain regions on the main surface of the semiconductor substrate using the gate electrode as a mask.

Abstract: Provided is a technology capable of improving the productivity of a p channel MISFET using a high dielectric-constant film as a gate insulating film and a conductive film containing metal as a gate electrode. In this technology, a threshold voltage of the p channel MISFET can be decreased even if a work function value of the conductive film containing metal at the time of contacting a silicon oxide film is away from a value near a valence band of silicon. A p channel MISFET formed on a semiconductor substrate has a gate insulating film formed of a hafnium oxide film, a metal oxide film formed of an aluminum oxide film on this gate insulating film, and a gate electrode formed of a tantalum nitride film on this metal oxide film. The metal oxide film has a function to shift a work function value of the gate electrode.

Abstract: A ruthenium electrode with a low amount of oxygen contamination and high thermal stability is formed by a chemical vapor deposition method. In the chemical vapor deposition method using an organoruthenium compound as a precursor, the introduction of an oxidation gas is limited to when the precursor is supplying, and the reaction is allowed to occur at a low oxygen partial pressure. Consequently, it is possible to form a ruthenium film with a low amount of oxygen contamination. Further, after formation of the ruthenium film, annealing at not less than the formation temperature is performed, thereby forming a ruthenium film with high thermal stability.

Abstract: An object of the present invention is to simplify manufacturing process of an n channel MIS transistor and a p channel MIS transistor with gate electrodes formed of a metal material. For its achievement, gate electrodes of each of the n channel MIS transistor and the p channel MIS transistor are simultaneously formed by patterning ruthenium film deposited on a gate insulator. Next, by introducing oxygen into each of the gate electrodes, the gate electrodes are transformed into those having high work function. Thereafter, by selectively reducing the gate electrode of the n channel MIS transistor, it is transformed into a gate electrode having low work function.

Abstract: A technology capable of improving the yield in a manufacturing process of a MISFET with a gate electrode formed of a metal silicide film. A gate insulating film is formed on a semiconductor substrate and silicon gate electrodes formed of a polysilicon film are formed on the gate insulating film. Then, after a silicon oxide film is formed so as to cover the silicon gate electrodes, a surface of the silicon oxide film is polished by CMP, thereby exposing the surface of the silicon gate electrodes. Subsequently, a patterned insulating film is formed on the silicon oxide film. Thereafter, an adhesion film is formed on the silicon oxide film and the insulating film. Then, a nickel film is formed on the adhesion film. Thereafter, a silicide reaction is caused to occur between the silicon gate electrode and the nickel film via the adhesion film.

Abstract: The performance and reliability of a semiconductor device are improved. In a semiconductor device having a CMISFET, a gate electrode of an n channel MISFET is composed of a nickel silicide film formed by reacting a silicon film doped with P, As, or Sb with an Ni film, and a gate electrode of a p channel MISFET is composed of a nickel-silicon-germanium film formed by reacting a nondope silicon germanium film with the Ni film. The work function of the gate electrode of the n channel MISFET is controlled by doping P, As, or Sb, and the work function of the gate electrode of the p channel MISFET is controlled by adjusting the Ge concentration.

Abstract: This invention provides a method for forming a semiconductor device, capable of preventing as many impurities as possible, which cause deterioration in film quality, from existing in an gate insulating film. In this invention, a step of forming an insulating film so as to have a thickness in the range of 0.3 to 2 nm and a step of removing impurities from the insulating film are repeated a plurality of times, to form an insulating film having a prescribed thickness.

Abstract: A method of forming a film on a substrate includes a first step of carrying out first film formation on an insulation layer formed on the substrate by an ALD process, and a second step of carrying out second film formation in continuation to the first step by a CVD process.

Abstract: As shown in FIG. 2B, a gate electrode is formed on a gate insulating film on a semiconductor substrate. A high dielectric film with a dielectric constant higher than that of a silicon oxide film is used for the gate insulating film, and a platinum-rich silicide film is used for the gate electrode. The platinum-rich silicide film indicates a film with a ratio of silicon atoms to platinum atoms of less than 1 (PtSix: x<1). Boron as a conductive impurity is introduced to the gate electrode composed of the platinum-rich silicide film, and the boron is segregated at an interface between the gate insulating film and the gate electrode.

Abstract: Threshold voltage of a CMOS transistor which uses a gate insulator made of a hafnium-based high-k material is optimized. A gate insulator of nMOS and pMOS transistors includes a HfOx film and a HfAlOx film formed thereon. At this time, silicon atoms in a n type polycrystalline silicon film which constitutes a gate electrode and Hf atoms in the HfAlOx film are bonded (Hf—Si bonding) and silicon atoms in the n type polycrystalline silicon film and Al atoms in the HfAlOx film are bonded (Al—O—Si bonding) at the interface between the HfAlOx film and the gate electrode. Consequently, the work function of the n type polycrystalline silicon and the work function of the p type polycrystalline silicon are controlled so as to be symmetrical with respect to a midgap (threshold voltage of MOS transistor=0) by changing the Al concentration in the HfAlOx film.

Abstract: A high dielectric gate insulating film having the structure that a high-nitrogen layer, a low-nitrogen layer, and a high-nitrogen layer are layered in this order from a silicon-substrate side.

Abstract: A metal atomic layer and an oxygen atomic layer are formed in this order by ALD, followed by rapid heating through RTA (Rapid Thermal Annealing). This cycle of steps is repeated to form a high dielectric constant film.

Abstract: This invention may provide a method and apparatus for forming a metal oxide thin film which is capable of forming metal oxide thin films of diverse kinds including, in particular, a compound metal oxide thin film comprising different kinds of metal by utilizing the ALD method without affecting the film forming speed. The method and apparatus may use a source gas containing a hydrolyzable metallic compound and an oxidizer gas containing a hydrate of a metal salt. The source gas and the oxidizer gas are alternately fed to reaction chamber (2) in which substrate (B) is placed with intervening purging with a purge gas, to form a metal oxide thin film on the substrate (B).

Abstract: A semiconductor device containing a dielectric capacitor having an excellent step coverage for a device structure of high aspect ratio corresponding to high integration degree, as well as a manufacturing method therefor are provided. A dielectric capacitor of high integration degree is manufactured by forming a bottom electrode 46 and a top-electrode 48 comprising a homogeneous thin Ru film with 100% step coverage while putting a dielectric 47 therebetween on substrates 44, 45 having a three-dimensional structure with an aspect ratio of 3 or more by a MOCVD process using a cyclopentadienyl complex within a temperature range from 180° C. or higher to 250° C. or lower.

Abstract: The manufacturing process of a semiconductor device in which a n channel MIS transistor and a p channel MIS transistor each having a gate electrode made of a metal material formed on a gate insulator made of a high dielectric constant material are used to form a CMOS circuit is simplified. After simultaneously forming the gate electrodes of the n channel MIS transistor and the p channel MIS transistor by patterning a platinum film deposited on a gate insulator made of a hafnium oxide film, only the gate insulator on the side of the n channel MIS transistor is selectively reduced by using the catalytic reduction of the platinum film. By doing so, the work function of the gate electrode of the n channel MIS transistor is changed.

Abstract: A structure of a MIS transistor for realizing a CMOS circuit capable of simultaneously achieving the high ON current and the low power consumption is provided. Each of the gate insulators of a n channel MIS transistor and a p channel MIS transistor is composed of a hafnium oxide film. Also, the gate electrode is composed of a Pt silicide film with a ratio of Si atoms to Pt atoms of approximately 1 (PtSix: x=1) in the vicinity of a region in contact with the gate insulator. Also, the gate electrode of the p channel MIS transistor is composed of a Pt silicide film with a ratio of Si atoms to Pt atoms of less than 1 (PtSix: x<1) in the vicinity of a region in contact with the gate insulator. Therefore, the Fermi level pinning of the gate electrode is suppressed.