Patents by Inventor Toshihiko Okamura

Toshihiko Okamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220021438
    Abstract: A wireless communication system includes a wireless sensor provided inside a metal housing; a receiver provided outside the metal housing to receive radio waves from the wireless sensor; and a passive repeater provided between the inside and the outside of the metal housing. The passive repeater includes a receiving antenna provided inside the metal housing and a transmitting antenna provided outside the metal housing. The receiving antenna of the passive repeater and the transmitting antenna of the passive repeater are electrically connected through a hole formed in the metal housing.
    Type: Application
    Filed: September 29, 2021
    Publication date: January 20, 2022
    Applicant: NSK LTD.
    Inventors: Keisuke Manabe, Toshihiko Okamura, Tomoyuki Yanagisawa
  • Patent number: 10408269
    Abstract: There is provided a wireless sensor-equipped bearing. A plurality of magnets are fixed between pockets of a retainer formed of an annular body such that an N pole and an S pole of the magnets neighbor in a circumferential direction of the annular body. A coil, a circuit unit and an antenna are fixed to a surface of a first seal, the surface being opposed to the magnets. A sensor is disposed on any one of an inner ring, an outer ring and the first seal.
    Type: Grant
    Filed: March 31, 2017
    Date of Patent: September 10, 2019
    Assignee: NSK Ltd.
    Inventors: Toshihiko Okamura, Kunihiko Sasao, Hideki Kobayashi
  • Publication number: 20190040912
    Abstract: There is provided a wireless sensor-equipped bearing. A plurality of magnets are fixed between pockets of a retainer formed of an annular body such that an N pole and an S pole of the magnets neighbor in a circumferential direction of the annular body. A coil, a circuit unit and an antenna are fixed to a surface of a first seal, the surface being opposed to the magnets. A sensor is disposed on any one of an inner ring, an outer ring and the first seal.
    Type: Application
    Filed: March 31, 2017
    Publication date: February 7, 2019
    Inventors: Toshihiko OKAMURA, Kunihiko SASAO, Hideki KOBAYASHI
  • Patent number: 10200356
    Abstract: An information processing system performing highly secure broadcast authentication while reducing a delay until authentication, a communication amount, and a computation amount is provided. A server (100) generates authentication information for transmission data by combining a tag relating to the transmission data and a chain value associated in a chain with transmission order of the transmission data. The tag relating to the transmission data is generated by using a common key. The chain is generated by using a one-way function. A node (200) verifies whether a chain value associated with transmission order of data received in the past is generated or not by applying the one-way function to a chain value extracted by using a tag relating to the received data and authentication information for the received data. The tag relating to the received data is generated by using the common key.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: February 5, 2019
    Assignee: NEC CORPORATION
    Inventor: Toshihiko Okamura
  • Publication number: 20170318002
    Abstract: An information processing system performing highly secure broadcast authentication while reducing a delay until authentication, a communication amount, and a computation amount is provided. A server (100) generates authentication information for transmission data by combining a tag relating to the transmission data and a chain value associated in a chain with transmission order of the transmission data. The tag relating to the transmission data is generated by using a common key. The chain is generated by using a one-way function. A node (200) verifies whether a chain value associated with transmission order of data received in the past is generated or not by applying the one-way function to a chain value extracted by using a tag relating to the received data and authentication information for the received data. The tag relating to the received data is generated by using the common key.
    Type: Application
    Filed: October 20, 2015
    Publication date: November 2, 2017
    Applicant: NEC CORPORATION
    Inventor: Toshihiko OKAMURA
  • Publication number: 20150304293
    Abstract: The message authentication system is a message authentication system used in a multihop network and including a server 30 and multiple nodes 1 which transmit data to the server 30. Each of the nodes 1 includes: a tag generation unit 902 which uses a private key shared with the server to calculate a tag as a message authenticator corresponding to the data; and a parity tag generation unit 901 which uses the tag to generate a parity tag composed of parities calculated as error-correcting code. The node 1 generates the parity tag corresponding to the tags created by the node 1 and child nodes of the node 1, and transmits the parity tag to a parent node or the server 30 together with the data.
    Type: Application
    Filed: November 7, 2013
    Publication date: October 22, 2015
    Applicant: NEC Corporation
    Inventor: Toshihiko OKAMURA
  • Publication number: 20140137211
    Abstract: The present invention has: a dynamic random access memory (DRAM); a refresh controller that receives information related to a range of the number of lost bits that are lost by stopping refresh processing of the DRAM, and controls a time to stop the refresh processing to achieve the range of the number of lost bits; and a physical information mapping unit that generates device specific information based on position information of the lost bits generated by stopping the refresh processing. It is preferable that the refresh controller corrects the time to stop the refresh processing based on the number of current lost bits to achieve the range of the number of lost bits set.
    Type: Application
    Filed: June 27, 2012
    Publication date: May 15, 2014
    Applicant: NEC CORPORATION
    Inventors: Kazuhiko Minematsu, Toshihiko Okamura, Yukiyasu Tsunoo
  • Patent number: 8627168
    Abstract: A multistage difference cyclic permutation unit (106) for performing multistage cyclic permutation, an address administration unit (104) for administering addresses of the cumulative LLR memory (101), a received value arrangement unit (103) for generating records during writing of received values to the cumulative LLR memory (101), and a control unit (110) for generating parameters to control each unit from information of a parity check matrix and the current cyclic permutation size are prepared. The address administration unit (104) controls reading/writing addresses of the cumulative LLR memory (101) based on a reading start address from the cumulative LLR memory (101) corresponding to the column block. After the start of reading of a column block, the control unit (110) generates a reading start address in the next decoding of the column block and stores it into the address administration unit (104).
    Type: Grant
    Filed: March 4, 2010
    Date of Patent: January 7, 2014
    Assignee: NEC Corporation
    Inventor: Toshihiko Okamura
  • Patent number: 8386877
    Abstract: Intended is to achieve, in a wide range of an SN ratio, throughput on the same order of that attained by a method based on puncturing and improve computational complexity of decoding processing at a high coding rate. In a communication system for transmitting an error correcting code for an error on a communication path from a transmitter to a receiver, the transmitter divides information bits of a code word to be transmitted into a plurality of blocks based on a request for retransmission of an error correcting code from the receiver, generates an error correcting code by compact-coding of one block among the plurality of blocks and transmits the generated error correcting code.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: February 26, 2013
    Assignee: NEC Corporation
    Inventor: Toshihiko Okamura
  • Publication number: 20130007568
    Abstract: Provided is an error correction code decoding apparatus capable of performing a decoding process efficiently for various interleaver sizes while suppressing an increase in apparatus size.
    Type: Application
    Filed: March 7, 2011
    Publication date: January 3, 2013
    Applicant: NEC CORPORATION
    Inventor: Toshihiko Okamura
  • Patent number: 8225174
    Abstract: To provide a decoder capable of efficiently dealing with various Z, even when in-block parallel degree is fixed in MP decoding of quasi-cyclic LDPC codes. A reception value aligning device keeps the first S or less reception value data from the block head. If block size Z is not a multiple of S, (S?(Z mod S)) data of the block head are added to the end of the reception value data of the block so that the block size Z is a multiple of S. The block size is written into reception value memory. A message aligning device performs cyclic permutation. If Z is not a multiple of S, the first (S?(Z mod S)) messages from the block output head are added to the end of the output message of the block so that the Z is a multiple of S and is outputted to the message memory.
    Type: Grant
    Filed: December 5, 2007
    Date of Patent: July 17, 2012
    Assignee: NEC Corporation
    Inventor: Toshihiko Okamura
  • Publication number: 20110320912
    Abstract: A multistage difference cyclic permutation means (106) for performing multistage cyclic permutation, an address administration means (104) for administering addresses of the cumulative LLR memory (101), a received value arrangement means (103) for generating records during writing of received values to the cumulative LLR memory (101), and a control means (110) for generating parameters to control each means from information of a parity check matrix and the current cyclic permutation size are prepared. The address administration means (104) controls reading/writing addresses of the cumulative LLR memory (101) based on a reading start address from the cumulative LLR memory (101) corresponding to the column block. After the start of reading of a column block, the control means (110) generates a reading start address in the next decoding of the column block and stores it into the address administration means (104).
    Type: Application
    Filed: March 4, 2010
    Publication date: December 29, 2011
    Applicant: NEC CORPORATION
    Inventor: Toshihiko Okamura
  • Publication number: 20100281327
    Abstract: Intended is to achieve, in a wide range of an SN ratio, throughput on the same order of that attained by a method based on puncturing and improve computational complexity of decoding processing at a high coding rate. In a communication system for transmitting an error correcting code for an error on a communication path from a transmitter to a receiver, the transmitter divides information bits of a code word to be transmitted into a plurality of blocks based on a request for retransmission of an error correcting code from the receiver, generates an error correcting code by compact-coding of one block among the plurality of blocks and transmits the generated error correcting code.
    Type: Application
    Filed: September 12, 2008
    Publication date: November 4, 2010
    Applicant: NEC CORPORATION
    Inventor: Toshihiko Okamura
  • Publication number: 20100017677
    Abstract: To provide a decoder capable of efficiently dealing with various Z, even when in-block parallel degree is fixed in MP decoding of quasi-cyclic LDPC codes. A reception value aligning device keeps the first S or less reception value data from the block head. If block size Z is not a multiple of S, (S?(Z mod S)) data of the block head are added to the end of the reception value data of the block so that the block size Z is a multiple of S. The block size is written into reception value memory. A message aligning device performs cyclic permutation. If Z is not a multiple of S, the first (S?(Z mod S)) messages from the block output head are added to the end of the output message of the block so that the Z is a multiple of S and is outputted to the message memory.
    Type: Application
    Filed: December 5, 2007
    Publication date: January 21, 2010
    Inventor: Toshihiko Okamura
  • Patent number: 7373581
    Abstract: A parallel decoder, which is simpler and more flexible than conventional devices, is provided in decoding device for a LDPC code. The present invention includes a plurality of memory units for storing a received value and a message generated during a Message-Passing decoding, a plurality of variable node function units, a plurality of check node function units, a plurality of address generation units for generating an address of each of memory units, and a plurality of shuffle network units for determining a connection between variable node function units and check node function units. An address generation unit generates an address on the basis of a plurality of permutations. Each shuffle network unit is connected to some of the variable node function units. This connection is determined on the basis of a plurality of permutations. A change of the permutations in the address generation units and a change of the permutations in the shuffle network units are performed in the same cycle in a decoding process.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: May 13, 2008
    Assignee: NEC Corporation
    Inventors: Toshihiko Okamura, Hiroaki Anada
  • Patent number: 7178090
    Abstract: In an error correction code decoding apparatus, utilized in the decoding of turbo codes, plural number of backward processing modules 100, 110 and 120 are provided. In one backward processing module, received data and a priori information are periodically read in the reverse order from memories 140 and 150 to calculate backward values. The other backward processing modules are supplied with received data and the a priori information, output from the preset other backward processing module to calculate backward values. The backward processing module reading in from the memories is cyclically changed. A forward processing and soft-output generating module 130 generates a soft-output by exploiting the backward values calculated by the backward processing module which lies directly ahead of the backward processing module reading in the data from the memories.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: February 13, 2007
    Assignee: NEC Corporation
    Inventors: Toshihiko Okamura, Hiroaki Anada
  • Publication number: 20040153938
    Abstract: A parallel decoder, which is simpler and more flexible than conventional devices, is provided in decoding device for a LDPC code. The present invention includes a plurality of memory units for storing a received value and a message generated during a Message-Passing decoding, a plurality of variable node function units, a plurality of check node function units, a plurality of address generation units for generating an address of each of memory units, and a plurality of shuffle network units for determining a connection between variable node function units and check node function units. An address generation unit generates an address on the basis of a plurality of permutations. Each shuffle network unit is connected to some of the variable node function units. This connection is determined on the basis of a plurality of permutations. A change of the permutations in the address generation units and a change of the permutations in the shuffle network units are performed in the same cycle in a decoding process.
    Type: Application
    Filed: November 26, 2003
    Publication date: August 5, 2004
    Applicant: NEC CORPORATION
    Inventors: Toshihiko Okamura, Hiroaki Anada
  • Publication number: 20030093753
    Abstract: In an error correction code decoding apparatus, utilized in the decoding of turbo codes, plural number of backward processing modules 100, 110 and 120 are provided. In one backward processing module, received data and a priori information are periodically read in the reverse order from memories 140 and 150 to calculate backward values. The other backward processing modules are supplied with received data and the a priori information, output from the preset other backward processing module to calculate backward values. The backward processing module reading in from the memories is cyclically changed. A forward processing and soft-output generating module 130 generates a soft-output by exploiting the backward values calculated by the backward processing module which lies directly ahead of the backward processing module reading in the data from the memories.
    Type: Application
    Filed: November 14, 2002
    Publication date: May 15, 2003
    Applicant: NEC CORPORATION
    Inventors: Toshihiko Okamura, Hiroaki Anada
  • Publication number: 20020094038
    Abstract: In a case where a soft input and soft output decoding method is applied to a decode processing carrying out repeated decode processing, preparing a plurality of kinds of block that is a unit of decode processing, setting the size of blocks that are initially processed for every kind of the repeated decode processing at different values of size.
    Type: Application
    Filed: August 31, 2001
    Publication date: July 18, 2002
    Applicant: NEC CORPORATION
    Inventor: Toshihiko Okamura
  • Patent number: 6122402
    Abstract: Pattern encoding is carried out by 1) substituting an index data of a registered pattern for a position data in a library with respect to an index data peculiar to each of the extracted patterns, 2) taking a difference between an off-set position data of the extracted pattern and an off-set position data of the registered pattern whereby an off-set position difference data is provided, and 3) encoding the position data and the off-set position difference data and providing an encoded data. A pattern extracting unit obtains the extracted patterns from image data. An accumulating/checking unit accumulates the extracted patterns as accumulated patterns, assigns indexes specific to the accumulated patterns, and checks each extracted pattern by comparison with the accumulated patterns. When an accumulated pattern is found to match the extracted pattern, the accumulating/checking unit provides a position data within a library instead of the index data, and also provides the off-set position difference data.
    Type: Grant
    Filed: December 3, 1997
    Date of Patent: September 19, 2000
    Assignee: NEC Corporation
    Inventors: Mitsutoshi Arai, Keiji Yamada, Toshihiko Okamura, Takahiro Hongu, Kouichirou Hirao