Abstract: Shift register stores data read from data memory through data bus, and supplies a shift output to shift register. Shift register stores operation target data read from data memory through data bus, shifts operation target data one bit by one bit, and supplies operation target data to bit selection circuit. Bit selection circuit selects bit data, which is placed at a position designated by register, from data stored in shift register. Multi-input exclusive OR circuit executes exclusive OR operations of all bits of bit data output from bit selection circuit, simultaneously, and outputs an operation result of one bit to shift register. This makes it possible to efficiently perform convolutional code processing at high speed.

Abstract: A silica-group composite oxide fiber formed of a composite oxide phase of an oxide phase (first phase) mainly made of a silica component and a metal oxide phase (second phase) excluding silica, in which the existent ratio of at least one metal element of a metal oxide constituting the second phase upward slopingly increases toward the surface layer of the fiber and a process for the production thereof.

Abstract: A headrest movable frame (2) has an upper frame (2b) which is arranged on the upper end face of a seatback and extends in the widthwise direction of the vehicle body, and side frames (10) which are arranged on the side end faces of the seatback and extend in the up-and-down direction. A lower frame (2c) is axially supported on the side frames (10) at a position below the upper frame (2b). Guide holes (3) linearly move a headrest (1) upward and forward by a backward load acting on the lower portion of the lower frame (2c) of the headrest movable frame (2) in a rear impact collision.

Abstract: Shift register 5 stores data read from data memory 1 through data bus 3, and supplies a shift output to shift register 4. Shift register 4 stores operation target data read from data memory 1 through data bus 3, shifts operation target data one bit by one bit, and supplies operation target data to bit selection circuit 7. Bit selection circuit 7 selects bit data, which is placed at a position designated by register 6, from data stored in shift register 4. Multi-input exclusive OR circuit 8 executes exclusive OR operations of all bits of bit data output from bit selection circuit 7, simultaneously, and outputs an operation result of one bit to shift register 9. This makes it possible to efficiently perform convolutional code processing at high speed.

Abstract: An air-bag 12 is designed to vertically expand after transversely expanding while being inflated. The air-bag 12 having a substantially circular shape is folded from its opposite ends toward its middle along a direction “a” corresponding to vertical direction and rolled in an opposite direction, is then folded in a zigzag manner one fold over another from its opposite ends toward its middle along a direction “b” (transverse direction), and is accommodated in a container casing 14. Accordingly, the inventive air-bag device and air-bag folding method can suppress an inflation (expansion) of the air-bag toward a passenger at an early stage of the inflation of the air-bag, promote a transverse expansion more than a vertical expansion of the air-bag at the early stage of the inflation, and prevent a blow out of a gas toward the passenger.

Abstract: An air-bag 12 is designed to vertically expand after transversely expanding while being inflated. The air-bag 12 having a substantially circular shape is folded from its opposite ends toward its middle along a direction “a” corresponding to vertical direction and rolled in an opposite direction, is then folded in a zigzag manner one fold over another from its opposite ends toward its middle along a direction “b” (transverse direction), and is accommodated in a container casing 14. Accordingly, the inventive air-bag device and air-bag folding method can suppress an inflation (expansion) of the air-bag toward a passenger at an early stage of the inflation of the air-bag, promote a transverse expansion more than a vertical expansion of the air-bag at the early stage of the inflation, and prevent a blow out of a gas toward the passenger.

Abstract: A rectifying plate (53) is inserted between gas outlets of a first inflator (51a) and/or a second inflator (51b) and a diffuser (55), and is formed with a plurality of openings which have different areas and uniform gas flows released from the gas outlets, and the opening area corresponding to the inactive second inflator (51b) of the first and second inflators (51a, 51b) is larger than the opening area corresponding to the active first inflator (51a).

Abstract: A silica-group composite oxide fiber formed of a composite oxide phase of an oxide phase (first phase) mainly made of a silica component and a metal oxide phase (second phase) excluding silica, in which the existent ratio of at least one metal element of a metal oxide constituting the second phase upward slopingly increases toward the surface layer of the fiber and a process for the production thereof.

Abstract: An air bag system comprises a crash detector for detecting a crash of the vehicle, an inflator for generating pressurized gas in response to a detection of a crush, and an air bag located in front of a seat for which is inflated and expanded with the pressurized gas to a predetermined inflated configuration. A control unit controls actuation of the inflator in accordance with driving conditions and whether or not the passenger is fastened by the seat belt. Threshold values are provided such that the inflator provides high and low levels of gas pressure with which the air bag is inflated and expanded.

Abstract: A highly heat-resistant sintered SiC fiber bonded material free of a decrease in strength and less breakable at an ultra-high temperature over 1,400.degree. C., comprising inorganic fibers which are composed mainly of a sintered SiC crystal, contain at least one kind of metal atoms selected from the class consisting of metal atoms of the 2A, 3A and 3B groups of the periodic table and are bonded nearly in the close-packed structure and 1 to 50 nm boundary layers composed mainly of carbon which are present at the interface of fibers, the less breakable highly heat-resistant sintered SiC fiber-bonded material having a density of at least 2.7 g/cm.sup.3 and an elastic modulus of at least 200 GPa, and a process for the production thereof.

Abstract: An arithmetic apparatus comprising a memory 1 for storing path select signals, a barrel shifter 3 for shifting data read from the memory, a shift register 4 for receiving a bit shifted to a MSB by the barrel shifter and means 5 for generating the number of shifts which are performed by the barrel shifter by converting data positioned at a specific bit position in the shift register, wherein path select signals at the same time are divided into a plurality of groups, and then stored in the memory, and the arithmetic apparatus includes address generating means 10 for outputting the address, and address conversion means 7 for generating the address of the group which must be read by combining the address and a value of a specific bit position in the shift register with each other. Thus, tracing back in Viterbi decoding can be performed with a short bit width.

Abstract: A silicon-carbide-based inorganic fiber not only excellent in mechanical properties but also excellent in alkali durability and heat resistance, containing at least 0.1% by weight of a metal atom which is at least one member selected from the group consisting of metals belonging to Groups 2A, 3A and 3B of the periodic table and whose oxide exhibits amphoterism or basicity, having an oxygen content of 17% by weight or less, having an atomic ratio of carbon to silicon (C/Si) in the range of from 1 to 1.7, and having a density of less than 2.7 g/cm.sup.3.

Abstract: A crystalline silicon carbide fiber excellent not only in mechanical properties but also in alkali durability at high temperatures, which has a density of at least 2.7 g/cm.sup.3, contains 55 to 70% by weight of Si, 30 to 45% by weight of C, 0.06 to 3.8% by weight of Al and 0.06 to 0.5% by weight of B, the total of these elements being 100% by weight, and has a sintered structure of SiC.

Abstract: An arithmetic apparatus in which while data read out of a memory is shifted by means of a barrel shifter by a shift bit number designated by data standing for an output signal of an inverter, data standing for an output signal of the barrel shifter is inputted to a shift register to thereby perform Viterbi decoding at a high speed.

Abstract: An obstacle detection system for vehicles detects kinetic attributes relative to a vehicle equipped with the system of an object present in a forward path of travel of the vehicle, sets a presumed zone into which the object is expected to have entered at a lapse of a specified period based on the kinetic attributes, and proves an object detected at a lapse of the specified period as the object previously detected if the object of second detection is determined as one having moved into the presumed zone and an obstacle precarious to the vehicle.

Abstract: A fixed-point arithmetic unit has a calculation controller for detecting number of significant bits of data to be calculated and controlling an adder so as to inhibit it from transferring a carry to a portion of the adder unnecessary for calculation of the significant bits and a register controller for controlling a register adapted to store input and output of the adder such that only the significant bits of data are stored in the register, whereby when the significant bits of data is smaller than a bit width of the arithmetic circuit, consumptive power of the arithmetic unit can be reduced.

Abstract: The present invention discloses a pipeline processor system comprising a pipeline processor and a memory device, wherein the memory device is comprised of a memory unit for holding data and/or an instruction as well as being accessed to implement memory read operation or memory write operation in a clock cycle; and a data latch unit for latching data to be written into the memory unit, while the pipeline processor is comprised of an instruction detection unit for detecting from fetched instructions a first predetermined instruction which directs the latch of the data as well as a second predetermined instruction which directs write of the data at the data latch means into the memory means; and a latch control unit for controlling to latch operation results of the first predetermined instruction to the data latch unit when the predetermined instruction is detected by the instruction detection unit as well as controlling to write the data at the data latch unit into the memory unit when the second predetermined

Abstract: An interleaving memory system having a first memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, a second memory device including a 0-bank and a 1-bank for simultaneously outputting data at even-numbered addresses from the 0-bank and data at odd-numbered addresses from the 1-bank, and a holding device for holding data from one of the banks of one of the first memory device and the second memory device to delay an output of the data for 1/2 cycle time for sequential addressing. A controller controls first and second selection devices wherein the 0-bank and the 1-bank are alternatively selected when data is outputted either in an ascending order of consecutive addresses from the even-numbered addresses in the first or second memory devices, or in a descending order of consecutive addresses from the odd-numbered addresses in the first or second memory devices.

Abstract: An arithmetic unit includes an arithmetic and logic circuit having n bits and capable of controlling the execution of either addition or subtraction by responding to a signal indicative of a positive or negative sign of a result of one preceding calculation, a register of n bits for temporarily storing data delivered out of the arithmetic and logic circuit, a register of n bits for delivering a divisor to the arithmetic and logic circuit, a shift register of n stages for sequentially storing signals indicative of a positive or negative sign of results of calculation by the arithmetic and logic circuit, and a shifter for shifting data of the register by one bit to the left and inserting data of the most significant bit of the shift register into the least significant bit to provide an output which in turn is delivered to the arithmetic and logic circuit. A conventional shifter having a bit length of 2n can be replaced with the shifter having a bit length of n and the shift register having a bit length of n.

Abstract: An arithmetic apparatus includes an arithmetic logic unit for performing a given arithmetic operation of double precision data having a preselected number of bits, a first register storing results of the arithmetic operation of higher-order bits in the double precision data, a second register storing results of the arithmetic operation of lower-order bits in the double precision data, an overflow-detection circuit for detecting overflow conditions of the results of the arithmetic operations, a maximum/minimum value-setting circuit for setting the results of the arithmetic operation to be stored in the first register to one of maximum and minimum values according to the overflow conditions, and a correction circuit for correcting an output value indicative of he results of the arithmetic operation provided by the second register to one of a first value defined by a bit sequence of 0s and a second value defined by a bit sequence of 1s according to the overflow condition.