Patents by Inventor Toshihiro Ohki

Toshihiro Ohki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150194512
    Abstract: A semiconductor device includes: a first semiconductor layer which is formed over a substrate and is formed from a nitride semiconductor; a second semiconductor layer which is formed over the first semiconductor layer and is formed from a nitride semiconductor; a third semiconductor layer which is formed over the second semiconductor layer and is formed from a nitride semiconductor; a source electrode and a drain electrode which are formed over the third semiconductor layer; an opening which is formed in the second semiconductor layer and the third semiconductor layer between the source electrode and the drain electrode; an insulating layer which is formed on a side surface and a bottom surface of the opening; and a gate electrode which is formed in the opening through the insulating layer.
    Type: Application
    Filed: December 4, 2014
    Publication date: July 9, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Toshihiro Ohki, LEI ZHU, NAOYA OKAMOTO, Yuichi Minoura, Shirou OZAKI
  • Publication number: 20150194514
    Abstract: On a surface of a compound semiconductor layer including inner wall surfaces of an electrode trench, an etching residue 12a and an altered substance 12b which are produced due to dry etching for forming the electrode trench are removed, and a compound semiconductor is terminated with fluorine. Gate metal is buried in the electrode trench via a gate insulating film, or the gate metal is directly buried in the electrode trench, whereby a gate electrode is formed.
    Type: Application
    Filed: March 9, 2015
    Publication date: July 9, 2015
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, Norikazu NAKAMURA, Toshihiro OHKI, Masahito KANAMURA
  • Patent number: 9035357
    Abstract: An HEMT includes, on an SiC substrate, a compound semiconductor layer, a silicon nitride (SiN) protective film having an opening and covering the compound semiconductor layer, and a gate electrode formed on the compound semiconductor layer so as to plug the opening. In the protective film, a projecting portion projecting from a side surface of the opening is formed at a lower layer portion 6a.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: May 19, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Naoya Okamoto, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Patent number: 9035353
    Abstract: A HEMT has a compound semiconductor layer, a protection film which has an opening and covers an upper side of the compound semiconductor layer, and a gate electrode which fills the opening and has a shape riding on the compound semiconductor layer, wherein the protection film has a stacked structure of a lower insulating film not containing oxygen and an upper insulating film containing oxygen, and the opening includes a first opening formed in the lower insulating film and a second opening formed in the upper insulating film and wider than the first opening, the first opening and the second opening communicating with each other.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: May 19, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Toshihiro Ohki, Naoya Okamoto, Yuichi Minoura, Kozo Makiyama, Shirou Ozaki
  • Patent number: 8969919
    Abstract: A field-effect transistor includes a carrier transport layer made of nitride semiconductor, a gate electrode having first and second sidewall surfaces on first and second sides, respectively, an insulating film formed directly on the gate electrode to cover at least one of the first and second sidewall surfaces, first and second ohmic electrodes formed on the first and second sides, respectively, a passivation film including a first portion extending from the first ohmic electrode toward the gate electrode to cover a surface area between the first ohmic electrode and the gate electrode and a second portion extending from the second ohmic electrode toward the gate electrode to cover a surface area between the second ohmic electrode and the gate electrode, wherein the insulating film is in direct contact with at least the first and second passivation film portions, and has a composition different from that of the passivation film.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Limited
    Inventors: Toshihiro Ohki, Naoya Okamoto
  • Publication number: 20140367694
    Abstract: A semiconductor device includes a first semiconductor layer configured to be formed of a nitride semiconductor on a substrate; a second semiconductor layer configured to be formed of a nitride semiconductor on the first semiconductor layer; an insulation film configured to include an opening, and to be formed on the second semiconductor layer; a source electrode and a drain electrode configured to be formed on the second semiconductor layer; and a gate electrode configured to be formed at the opening on the second semiconductor layer. Both the insulation film and the second semiconductor layer include carbon in a neighborhood of an interface between the insulation film and the second semiconductor layer.
    Type: Application
    Filed: June 11, 2014
    Publication date: December 18, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Youichi KAMADA, Shirou OZAKI, Toshihiro Ohki, Kozo Makiyama, NAOYA OKAMOTO
  • Publication number: 20140342513
    Abstract: A semiconductor apparatus includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a gate recess formed by removing at least a portion of the second semiconductor layer, an insulation film formed on the gate recess and the second semiconductor layer, a gate electrode formed on the gate recess via the insulation film, source and drain electrodes formed on one of the first and the second semiconductor layers, and a fluorine containing region formed in at least one of a part of the first semiconductor layer corresponding to a region in which the gate recess is formed and a part of the second semiconductor layer corresponding to the region in which the gate recess is formed.
    Type: Application
    Filed: August 4, 2014
    Publication date: November 20, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Toshihiro OHKI, Hiroshi ENDO
  • Patent number: 8883581
    Abstract: A compound semiconductor device includes a compound semiconductor composite structure in which two-dimensional electron gas is generated; and an electrode that is formed on the compound semiconductor composite structure, wherein the compound semiconductor composite structure includes a p-type semiconductor layer below a portion where the two-dimensional electron gas is generated, and the p-type semiconductor layer includes a portion containing a larger amount of an ionized acceptor than other portions of the p-type semiconductor layer, the portion being located below the electrode.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: November 11, 2014
    Assignee: Transphorm Japan, Inc.
    Inventor: Toshihiro Ohki
  • Patent number: 8866157
    Abstract: A semiconductor device may include a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a source electrode and a drain electrode in contact with the first semiconductor layer or the second semiconductor layer, an opening formed in the second semiconductor layer, an insulating film formed on an inner surface of the opening formed in the second semiconductor layer and above the second semiconductor layer, a gate electrode formed in the opening via the insulating film, and a protective film formed on the insulating film and including an amorphous film containing carbon as a major component.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 21, 2014
    Assignee: Fujitsu Limited
    Inventors: Norikazu Nakamura, Shirou Ozaki, Masayuki Takeda, Toyoo Miyajima, Toshihiro Ohki, Masahito Kanamura, Kenji Imanishi, Toshihide Kikkawa, Keiji Watanabe
  • Publication number: 20140306231
    Abstract: A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.
    Type: Application
    Filed: March 19, 2014
    Publication date: October 16, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, NAOYA OKAMOTO, Kozo Makiyama, Toshihiro Ohki
  • Publication number: 20140295666
    Abstract: A compound semiconductor device includes a compound semiconductor laminated structure, a passivation film formed on the compound semiconductor laminated structure and having a through-hole, and a gate electrode formed on the passivation film so as to plug the through-hole. A grain boundary between different crystalline orientations is formed in the gate electrode, and a starting point of the grain boundary is located apart from the through-hole on a flat surface of the passivation film.
    Type: Application
    Filed: June 11, 2014
    Publication date: October 2, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Patent number: 8829569
    Abstract: A semiconductor apparatus includes a first semiconductor layer formed on a substrate, a second semiconductor layer formed on the first semiconductor layer, a gate recess formed by removing at least a portion of the second semiconductor layer, an insulation film formed on the gate recess and the second semiconductor layer, a gate electrode formed on the gate recess via the insulation film, source and drain electrodes formed on one of the first and the second semiconductor layers, and a fluorine containing region formed in at least one of a part of the first semiconductor layer corresponding to a region in which the gate recess is formed and a part of the second semiconductor layer corresponding to the region in which the gate recess is formed.
    Type: Grant
    Filed: November 7, 2011
    Date of Patent: September 9, 2014
    Assignee: Fujitsu Limited
    Inventors: Toshihiro Ohki, Hiroshi Endo
  • Patent number: 8809136
    Abstract: A semiconductor device having a source electrode and a drain electrode formed over a semiconductor substrate, a gate electrode formed over the semiconductor substrate and disposed between the source electrode and the drain electrode, a protection film made of an insulating material and formed between the source electrode and the gate electrode and between the drain electrode and the gate electrode, and a gate side opening formed at least in one of a portion of the protection film-between the source electrode and the gate electrode and a portion of the protection film between the drain electrode and the gate electrode and disposed away from all of the gate electrode, the source electrode and the drain electrode.
    Type: Grant
    Filed: September 2, 2011
    Date of Patent: August 19, 2014
    Assignee: Fujitsu Limited
    Inventor: Toshihiro Ohki
  • Patent number: 8791465
    Abstract: A compound semiconductor device includes a compound semiconductor laminated structure, a passivation film formed on the compound semiconductor laminated structure and having a through-hole, and a gate electrode formed on the passivation film so as to plug the through-hole. A grain boundary between different crystalline orientations is formed in the gate electrode, and a starting point of the grain boundary is located apart from the through-hole on a flat surface of the passivation film.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Limited
    Inventors: Naoya Okamoto, Kozo Makiyama, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Publication number: 20140185347
    Abstract: An HEMT includes, on an SiC substrate, a compound semiconductor layer, a silicon nitride (SiN) protective film having an opening and covering the compound semiconductor layer, and a gate electrode formed on the compound semiconductor layer so as to plug the opening. In the protective film, a projecting portion projecting from a side surface of the opening is formed at a lower layer portion 6a.
    Type: Application
    Filed: March 10, 2014
    Publication date: July 3, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Kozo Makiyama, Naoya Okamoto, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Publication number: 20140151748
    Abstract: The compound semiconductor device includes a first-compound-semiconductor-layer, a second-compound-semiconductor-layer formed on an upper side of the first-compound-semiconductor-layer and having a band gap larger than the band gap of the first-compound-semiconductor-layer, a p-type third-compound-semiconductor-layer formed on an upper side of the second-compound-semiconductor-layer, an electrode formed on an upper side of the second-compound-semiconductor-layer through the third-compound-semiconductor-layer, a fourth-compound-semiconductor-layer formed so as to be in contact with the third-compound-semiconductor-layer at an upper side of the second-compound-semiconductor-layer and having a band gap smaller than the band gap of the second-compound-semiconductor-layer, and a fifth-compound-semiconductor-layer formed so as to be in contact with the third-compound-semiconductor-layer at an upper side of the fourth-compound-semiconductor-layer and having a band gap larger than the band gap of the fourth-compound-
    Type: Application
    Filed: October 29, 2013
    Publication date: June 5, 2014
    Applicant: Fujitsu Limited
    Inventors: Masato Nishimori, Tadahiro Imada, Toshihiro Ohki
  • Patent number: 8715213
    Abstract: The present invention has as an object to provide a bone metabolism improving agent that improves bone metabolism in a chronic renal failure patient receiving blood purification therapy such as hemodialysis, hemofiltration and hemodiafiltration. An acetic acid- and/or acetate salt-free bone metabolism improving agent that contains citric acid and/or a citrate salt as electrolytes and further contains another/other electrolyte/electrolytes and glucose solely or in combination is provided. A bone metabolism improving agent formulated into a dialysate or a substitution fluid having effects of improving bone metabolism including bone metabolism improvement in adynamic bone disease and especially in bone agenesis is also provided.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: May 6, 2014
    Assignee: Ajinomoto Co., Inc.
    Inventors: Hidehiro Yamazaki, Toshihiro Ohki, Tomio Inaba, Naomi Sakaguchi
  • Patent number: 8709886
    Abstract: An HEMT includes, on an SiC substrate, a compound semiconductor layer, a silicon nitride (SiN) protective film having an opening and covering the compound semiconductor layer, and a gate electrode formed on the compound semiconductor layer so as to plug the opening. In the protective film, a projecting portion projecting from a side surface of the opening is formed at a lower layer portion 6a.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: April 29, 2014
    Assignee: Fujitsu Limited
    Inventors: Kozo Makiyama, Naoya Okamoto, Toshihiro Ohki, Yuichi Minoura, Shirou Ozaki, Toyoo Miyajima
  • Publication number: 20140084339
    Abstract: A compound semiconductor device includes as compound semiconductor layers: a first layer; a second layer larger in band gap than the first layer, formed above the first layer; a third layer having a p-type conductivity type, formed above the second layer; a gate electrode formed above the second layer via the third layer; a fourth layer larger in band gap than the second layer, formed to be in contact with the third layer above the second layer; and a fifth layer smaller in band gap than the fourth layer, formed to be in contact with the third layer above the fourth layer.
    Type: Application
    Filed: July 16, 2013
    Publication date: March 27, 2014
    Inventors: Masato NISHIMORI, Tadahiro IMADA, Toshihiro OHKI
  • Publication number: 20140084345
    Abstract: A compound semiconductor device includes: a compound semiconductor stacked structure; a source electrode and a drain electrode formed separately from each other above the compound semiconductor stacked structure; a gate electrode formed between the source electrode and the drain electrode above the compound semiconductor stacked structure; and a passivation film formed above the compound semiconductor stacked structure and made of an insulating material containing Al, in which the passivation film is in a non-contact state with the compound semiconductor stacked structure under the source electrode and the drain electrode.
    Type: Application
    Filed: September 18, 2013
    Publication date: March 27, 2014
    Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITED
    Inventors: Toshihiro Ohki, YUUICHI SATOU