Patents by Inventor Toshiji Miyasaka

Toshiji Miyasaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9048242
    Abstract: In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.
    Type: Grant
    Filed: June 16, 2011
    Date of Patent: June 2, 2015
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Akio Horiuchi, Toshiji Miyasaka
  • Patent number: 8609998
    Abstract: A wiring board (package) has a structure in which multiple wiring layers are stacked one on top of another with insulating layers each interposed between corresponding two of the wiring layers, and the wiring layers are connected to one another through vias formed in each of the insulating layers. In a peripheral region of the package, reinforcing patterns are provided on the same surfaces where the corresponding wiring layers are provided, respectively. Each of the reinforcing patterns is formed of a conductive layer formed on the same surface where the corresponding one of the wiring layers is provided, and is provided in an intermittent ring-like shape when viewed in a planar view.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: December 17, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Toshiji Miyasaka, Akio Horiuchi
  • Patent number: 8217509
    Abstract: In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.
    Type: Grant
    Filed: February 17, 2009
    Date of Patent: July 10, 2012
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Akio Horiuchi, Toshiji Miyasaka
  • Publication number: 20110244631
    Abstract: In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.
    Type: Application
    Filed: June 16, 2011
    Publication date: October 6, 2011
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Akio HORIUCHI, Toshiji MIYASAKA
  • Publication number: 20100175917
    Abstract: A wiring board (package) has a structure in which multiple wiring layers are stacked one on top of another with insulating layers each interposed between corresponding two of the wiring layers, and the wiring layers are connected to one another through vias formed in each of the insulating layers. In a peripheral region of the package, reinforcing patterns are provided on the same surfaces where the corresponding wiring layers are provided, respectively. Each of the reinforcing patterns is formed of a conductive layer formed on the same surface where the corresponding one of the wiring layers is provided, and is provided in an intermittent ring-like shape when viewed in a planar view.
    Type: Application
    Filed: January 13, 2010
    Publication date: July 15, 2010
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Toshiji MIYASAKA, Akio Horiuchi
  • Publication number: 20090206470
    Abstract: In a semiconductor device manufacturing method, a semiconductor chip is mounted on a support board so as to expose a side of the semiconductor chip on which a plurality of terminal electrodes are provided. An insulating layer is formed so as to cover the side of the semiconductor chip on which the terminal electrodes are provided. Through electrodes connecting to the terminal electrodes and piercing the insulating layer are formed. Metal wirings connecting to the through electrodes are formed on the insulating layer. External terminal electrodes connecting the metal wiring are formed. Second spacing, spacing between the adjacent external terminal electrodes, is larger than first spacing, spacing between the adjacent terminal electrodes.
    Type: Application
    Filed: February 17, 2009
    Publication date: August 20, 2009
    Applicant: Shinko Electric Industries, Co., Ltd.
    Inventors: Akio Horiuchi, Toshiji Miyasaka