Patents by Inventor Toshikatsu Hida

Toshikatsu Hida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210286671
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, a random access memory and a controller. When writing n?1 data portions of a first unit that are included in n?1 error correction code frames of a first size, respectively, in the nonvolatile memory, the controller generates a second error correction code that constitutes an error correction code frame of a second size together with the n?1 data portions of the first unit and a second data portion to be written into the nonvolatile memory by encoding the n?1 data portions of the first unit and the second data portion, and writes the second data portion and the second error correction code into the nonvolatile memory.
    Type: Application
    Filed: March 11, 2021
    Publication date: September 16, 2021
    Applicant: Kioxia Corporation
    Inventors: Takehiko AMAKI, Toshikatsu HIDA, Shunichi IGAHARA, Yoshihisa KOJIMA, Suguru NISHIKAWA
  • Patent number: 11086718
    Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: August 10, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Riki Suzuki, Toshikatsu Hida, Yoshihisa Kojima, Takehiko Amaki, Suguru Nishikawa
  • Patent number: 11055215
    Abstract: A memory system includes a nonvolatile memory that has a plurality of physical blocks, and a memory controller circuit configured to execute encoding of data to be written in the nonvolatile memory and decoding of data read from the nonvolatile memory, execute garbage collection for the nonvolatile memory, and determine whether or not decoding and encoding is to be executed, for data which is read from a valid cluster of a physical block targeted for garbage collection.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 6, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takehiko Amaki, Toshikatsu Hida
  • Patent number: 11042310
    Abstract: A memory system includes a nonvolatile semiconductor memory including a first memory region for storing start-up information and a second memory region for storing a copy of the start-up information, a volatile semiconductor memory, and a controller. The controller is configured to determine whether or not an address of the second memory region is stored in the volatile semiconductor memory, issue a first start-up read command, which designates no read address, to the nonvolatile semiconductor memory to read the start-up information from the first memory region if the address of the second memory region is not stored in the volatile semiconductor memory, and issue a second start-up read command, which designates the address of the second memory region as a read address, to read the start-up information from the second memory region if the address of the second memory region is stored in the volatile semiconductor memory.
    Type: Grant
    Filed: July 9, 2019
    Date of Patent: June 22, 2021
    Assignee: KIOXIA CORPORATION
    Inventors: Riki Suzuki, Toshikatsu Hida, Takehiko Amaki, Shunichi Igahara
  • Publication number: 20210183877
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
    Type: Application
    Filed: February 23, 2021
    Publication date: June 17, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Takehiko AMAKI, Yoshihisa KOJIMA, Toshikatsu HIDA, Marie Grace Izabelle Angeles SIA, Riki SUZUKI, Shohei ASAMI
  • Publication number: 20210175907
    Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 10, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Riki SUZUKI, Toshikatsu HIDA, Osamu TORII, Hiroshi YAO, Kiyotaka IWASAKI
  • Patent number: 10964712
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes blocks each containing memory cells. The controller is configured to instruct the semiconductor memory to execute a first operation and a second operation. In the first operation and the second operation, the semiconductor memory selects at least one of the blocks, and applies at least one voltage to all memory cells contained in said selected blocks. A number of blocks to which said voltage is applied per unit time in the second operation is larger than that in the first operation.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: March 30, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takehiko Amaki, Yoshihisa Kojima, Toshikatsu Hida, Marie Grace Izabelle Angeles Sia, Riki Suzuki, Shohei Asami
  • Patent number: 10965324
    Abstract: According to one embodiment, a nonvolatile memory includes a plurality of memory areas and controller circuit including an error correction code encoder. The error correction code encoder encodes a first data to generate a first parity in a first operation and encodes a second data to generate a second parity in a second operation. The controller circuit writes the first data and the first parity into a first memory area among the plurality of memory areas and writes the second data and the second parity into a second memory area among the plurality of memory areas. The size of the second data is smaller than the size of the first data and the size of the second parity is equal to the size of the first parity.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: March 30, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Riki Suzuki, Toshikatsu Hida, Osamu Torii, Hiroshi Yao, Kiyotaka Iwasaki
  • Publication number: 20210081276
    Abstract: A memory system includes a nonvolatile memory, a buffer, and a controller. The buffer can temporarily store a plurality of data bits to be written to the nonvolatile memory. The controller can write the plurality of data bits, read from the buffer, to the nonvolatile memory; write a plurality of intermediate parity bits to the buffer, but not to the nonvolatile memory, wherein each of the plurality of intermediate parity bits is associated with an error correction process on each of the plurality of data bits; and write, to the nonvolatile memory, an accumulated parity bit that is an integration of the plurality of intermediate parity bits.
    Type: Application
    Filed: March 2, 2020
    Publication date: March 18, 2021
    Applicant: KIOXIA CORPORATION
    Inventors: Riki SUZUKI, Toshikatsu HIDA, Yoshihisa KOJIMA, Takehiko AMAKI, Suguru NISHIKAWA
  • Publication number: 20210073119
    Abstract: According to one embodiment, a memory system includes a non-volatile memory including first and second block groups, and a controller that performs a first write operation for the first block group and the first or a second write operation for the second block group. A first or second number of bits is written into a memory cell in the first or the second write operation. The second number of bits is larger than the first number of bits. The controller allocates a block to a buffer as a write destination block in the first write operation based on a degree of wear-out of at least one block, and writes data from an external device into the buffer in the first write operation.
    Type: Application
    Filed: March 3, 2020
    Publication date: March 11, 2021
    Applicant: Kioxia Corporation
    Inventors: Takehiko AMAKI, Toshikatsu HIDA, Shunichi IGAHARA, Yoshihisa KOJIMA, Suguru NISHIKAWA
  • Publication number: 20210042034
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 11, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
  • Patent number: 10908659
    Abstract: A memory system includes a nonvolatile memory and a memory controller. The memory controller is configured to execute a process to adjust a temperature of the nonvolatile memory upon determining that the temperature is outside a preferred range.
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: February 2, 2021
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Yuka Kuwano, Takehiko Amaki, Toshikatsu Hida, Shohei Asami
  • Patent number: 10895990
    Abstract: According to one embodiment, a memory system includes a first memory as a nonvolatile memory storing first data, second data as a translation table for accessing the first data, third data, fourth data as a translation table for accessing the third data, and including two memory cell arrays which are accessible in parallel, a second memory in which the second and fourth data is storable, and which stores a management table for managing information about whether the second and fourth data is stored in the second memory, a controller checking whether the second and fourth data is stored in the second memory based on the management table, a third memory storing an order of executing commands to be issued to the first memory, and a scheduler scheduling the order based on a result of the checking, two of a first command for reading the first data, a second command for reading the second data, a third command for reading the third data and a fourth command for reading the fourth data being executed in parallel in t
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: January 19, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Sayano Aga, Toshikatsu Hida, Riki Suzuki
  • Publication number: 20210004169
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.
    Type: Application
    Filed: September 22, 2020
    Publication date: January 7, 2021
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Shunichi Igahara, Toshikatsu Hida, Riki Suzuki, Takehiko Amaki, Suguru Nishikawa, Yoshihisa Kojima
  • Publication number: 20210005264
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Suguru NISHIKAWA, Yoshihisa KOJIMA, Riki SUZUKI, Masanobu SHIRAKAWA, Toshikatsu HIDA
  • Patent number: 10845992
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 24, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • Patent number: 10831395
    Abstract: According to one embodiment, a memory system includes a memory and a controller electrically connected to the memory. The memory includes blocks. Each of the blocks includes one or more sub-blocks. Each of the one or more sub-blocks includes nonvolatile memory cells. The controller is configured to obtain read frequency of at least one of the sub-blocks, and move data stored in the at least one of the sub-blocks so that data having substantially the same read frequency are written into one block.
    Type: Grant
    Filed: December 7, 2018
    Date of Patent: November 10, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Riki Suzuki, Yoshihisa Kojima, Toshikatsu Hida
  • Patent number: 10824353
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller electrically connected to the nonvolatile memory. The controller selects a write mode from a first mode in which data having N bits is written per one memory cell and a second mode in which data having M bits is written per one memory cell. N is equal to or larger than one. M is larger than N. The controller writes data into the nonvolatile memory in the selected write mode. The controller selects either the first mode or the second mode at least based on a total number of logical addresses mapped in a physical address space of the nonvolatile memory.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: November 3, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Shunichi Igahara, Toshikatsu Hida, Riki Suzuki, Takehiko Amaki, Suguru Nishikawa, Yoshihisa Kojima
  • Patent number: 10818358
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor memory, and a controller. The semiconductor memory includes a memory cell, and a write circuit configured to write data to the memory cell by applying a program voltage to the memory cell and comparing a threshold voltage of the memory cell with a first reference voltage corresponding to the write data. The write circuit is configured to execute a first programming operation to obtain a value of a write parameter by comparing the threshold voltage with a second reference voltage different from the first reference voltage.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: October 27, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Suguru Nishikawa, Yoshihisa Kojima, Riki Suzuki, Masanobu Shirakawa, Toshikatsu Hida
  • Patent number: 10803930
    Abstract: According to one embodiment, a memory system comprising includes a semiconductor memory and a memory controller. The memory controller is configured to obtain first data read from the semiconductor memory using a first voltage, obtain second data read from the semiconductor memory using a second voltage, calculate a first value for a first section of the first data using the first data and the second data, calculate a second value for a second section of the first data using the first data and the second data, calculate a third value for a third section of the first data using the first data and the second data, and correct an error of the first data using the first to third values.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: October 13, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Masahiro Kiyooka, Yoshihisa Kojima, Toshikatsu Hida