Patents by Inventor Toshiki Kimura

Toshiki Kimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804950
    Abstract: A SAW device includes a piezoelectric substrate, a support substrate which is located on a lower surface of the piezoelectric substrate and has a smaller thermal expansion coefficient than that of the piezoelectric substrate, an IDT electrode located on the piezoelectric substrate, a cover forming a space above the IDT electrode, and a plurality of first strip conductors which extend alongside each other on the cover and at least a part of which overlaps the space when viewed on a plane.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: October 13, 2020
    Assignee: KYOCERA Corporation
    Inventors: Toshiya Kimura, Masaki Nambu, Masaru Nagata, Toshiki Matsuoka
  • Patent number: 10784186
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin for sealing the semic
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 22, 2020
    Assignee: KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
  • Patent number: 10777489
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: September 15, 2020
    Assignee: KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
  • Publication number: 20200106469
    Abstract: A SAW device includes a piezoelectric substrate, a support substrate which is located on a lower surface of the piezoelectric substrate and has a smaller thermal expansion coefficient than that of the piezoelectric substrate, an IDT electrode located on the piezoelectric substrate, a cover forming a space above the IDT electrode, and a plurality of first strip conductors which extend alongside each other on the cover and at least a part of which overlaps the space when viewed on a plane.
    Type: Application
    Filed: March 20, 2018
    Publication date: April 2, 2020
    Inventors: Toshiya KIMURA, Masaki NAMBU, Masaru NAGATA, Toshiki MATSUOKA
  • Patent number: 10600725
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: March 24, 2020
    Assignees: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD., KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
  • Publication number: 20200023737
    Abstract: A vehicle display device pointer includes a translucent pointer that has a pointer main body disposed on a front side of a dial plate having a penetration hole and extending along the dial plate, a shaft protruding toward the penetration hole, and a light guide connecting the pointer main body and the shaft; a lightproof first shielding member that covers a proximal end portion of the pointer main body and the light guide from a front side and a lateral side; and a lightproof second shielding member that covers the proximal end portion of the pointer main body and the light guide from the back side. The pointer main body emits light by light emitted from a light source and incident on the shaft, and the second shielding member has protrusions that protrude toward the front side, and close gaps.
    Type: Application
    Filed: June 27, 2019
    Publication date: January 23, 2020
    Inventors: Hiromichi Kimura, Toshiki Kobayashi, Mao Nakashima, Akihiro Yatsuzuka
  • Patent number: 10505030
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, and first to third semiconductor regions. The third electrode is separated from the second electrode in a first direction. The first semiconductor region includes a first partial region separated from the first electrode, a second partial region separated from the second electrode, and a third partial region separated from the third electrode. The second semiconductor region includes a fourth partial region positioned between the first electrode and the first partial region, a fifth partial region positioned between the second electrode and the second partial region, and a sixth partial region positioned between the third electrode and the third partial region. The third semiconductor region includes a seventh partial region positioned between the second electrode and the fifth partial region and an eighth partial region positioned between the third electrode and the sixth partial region.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: December 10, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue, Masahiko Kuraguchi
  • Publication number: 20190371709
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first clip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame; and a sealing resin for sealing the semic
    Type: Application
    Filed: October 16, 2018
    Publication date: December 5, 2019
    Applicant: KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi URUSHIHATA, Takashi SHIGENO, Eiki ITO, Wataru KIMURA, Hirotaka ENDO, Toshio KOIKE, Toshiki KOUNO
  • Publication number: 20190371712
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, the semiconductor chip having an upper surface on which a first electrode is disposed and a lower surface on which a second electrode is disposed; a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; and a sealing resin for sealing the semiconductor chip, the die pad frame, and the conductive connection member for die pad.
    Type: Application
    Filed: October 16, 2018
    Publication date: December 5, 2019
    Applicant: Katoh Electric Co., Ltd.
    Inventors: Hiroyoshi Urushihata, Takashi Shigeno, Eiki Ito, Wataru Kimura, Hirotaka Endo, Toshio Koike, Toshiki Kouno
  • Publication number: 20190371710
    Abstract: A semiconductor module includes a die pad frame; a semiconductor chip disposed in a chip region on an upper surface of the die pad frame, a conductive connection member for die pad disposed between the second electrode of the semiconductor chip and the upper surface of the die pad frame, the conductive connection member for die pad electrically connecting the second electrode of the semiconductor chip and the upper surface of the die pad frame; a first clip frame disposed on the upper surface of the semiconductor chip; a first dip conductive connection member disposed between the first electrode on the semiconductor chip and a lower surface of the first clip frame, the first clip conductive connection member electrically connecting the first electrode of the semiconductor chip and the lower surface of the first clip frame and a sealing resin.
    Type: Application
    Filed: May 29, 2018
    Publication date: December 5, 2019
    Applicants: SHINDENGEN ELECTRIC MANUFACTURING CO., LTD., KATOH ELECTRIC CO., LTD.
    Inventors: Hiroyoshi URUSHIHATA, Takashi SHIGENO, Eiki ITO, Wataru KIMURA, Hirotaka ENDO, Toshio KOIKE, Toshiki KOUNO
  • Patent number: 10483354
    Abstract: In one embodiment, a nitride semiconductor device is provided with a first semiconductor layer that is a layer of Alx1Ga(1-x1)N (0<x1?1), a second semiconductor layer that is on the first semiconductor layer and is a layer of a nitride semiconductor Iny2Alx2Ga(1-x2-y2)N (0<x2<1, 0<y2<1, 0<x2+y2?1) containing indium, a third semiconductor layer that is on the second semiconductor layer and is a layer of Alx3Ga(1-x3)N (0?x3<1), and a fourth semiconductor layer that is on the third semiconductor layer and is an layer of Iny4Alx4Ga(1-x4-y4)N (0<x4<1, 0?y4<1, 0<x4+y4?1).
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: November 19, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kenjiro Uesugi, Shigeya Kimura, Toshiki Hikosaka
  • Patent number: 10475915
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating layer. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes at least one of Alx1Ga1-x1N (0<x1<1) or p-type Alz1Ga1-z1N (0?z1<1) and has a first surface, a second surface, and a third surface. The second layer includes Alx2Ga1-x2N (0?x2<1 and x2<x1) and includes a first partial region, a second partial region, and a third partial region. The third layer includes Alx3Ga1-x3N (0<x3<1 and x2<x3) and includes a fourth partial region, a fifth partial region, and a sixth partial region.
    Type: Grant
    Filed: March 20, 2019
    Date of Patent: November 12, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Jumpei Tajima, Toshiki Hikosaka, Kenjiro Uesugi, Shigeya Kimura, Masahiko Kuraguchi, Shinya Nunoue
  • Publication number: 20190276103
    Abstract: Disclosed is a work vehicle having a load carrier deck provided at a rear portion of a vehicle body to be vertically pivotable between an elevated discharging posture and a lowered load carrying posture. An engine section is provided under the load carrier deck. The engine section includes an engine, an exhaust muffler for the engine, and a muffler heat insulating cover for covering an outer circumference of the exhaust muffler. The muffler heat insulating cover is supported by a vehicle body frame via an anti-vibration member.
    Type: Application
    Filed: November 14, 2018
    Publication date: September 12, 2019
    Inventors: Toshiki Ono, Hiroki Bessho, Yuichiro Kimura, Rei Tokuda
  • Publication number: 20190276090
    Abstract: A work vehicle including: a vehicle body frame; a prime mover part located on a front or rear part of the vehicle body frame; a bonnet configured to open and close by swinging, and covering the prime mover part; and an assist unit configured to assist the bonnet to operate to open. A lateral end portion of the vehicle body frame is provided with a first linkage part with which the assist unit is linked. A lateral end portion of a lower end part of the bonnet, which is located closer to an end cover than the first linkage part is, is provided with a second linkage part with which the assist unit is linked. The assist unit is provided with an expansion/contraction mechanism biased so as to expand, and is located laterally outside the prime mover part and spans the first linkage part and the second linkage part.
    Type: Application
    Filed: May 29, 2019
    Publication date: September 12, 2019
    Inventors: Takeshi Komorida, Koichiro Matsumoto, Masaki Takaoka, Arisa Kimura, Tasuku Teraoka, Azusa Furihata, Tomohisa Yamamoto, Toshiki Kanai, Nobuyuki Yamashita, Masayuki Akita, Takashi Kumashiro, Ryo Matsumoto, Hiroki Nagai, Tatsuki Kago, Akihito Mihara
  • Publication number: 20190237550
    Abstract: In one embodiment, a nitride semiconductor device is provided with a first semiconductor layer that is a layer of Alx1Ga(1-x1)N (0<x1?1), a second semiconductor layer that is on the first semiconductor layer and is a layer of a nitride semiconductor Iny2Alx2Ga(1-x2-y2)N (0<x2<1, 0<y2<1, 0<x2+y2?1) containing indium, a third semiconductor layer that is on the second semiconductor layer and is a layer of Alx3Ga(1-x3)N (0?x3<1), and a fourth semiconductor layer that is on the third semiconductor layer and is an layer of Iny4Alx4Ga(1-x4-y4)N (0<x4<1, 0?y4<1, 0<x4+y4?1).
    Type: Application
    Filed: August 31, 2018
    Publication date: August 1, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Kenjiro Uesugi, Shigeya Kimura, Toshiki Hikosaka
  • Publication number: 20190214495
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a second electrode, a third electrode, a first layer, a second layer, a third layer, and an insulating layer. A position of the third electrode is between a position of the first electrode and a position of the second electrode. The first layer includes at least one of Alx1Ga1-x1N (0<x1<1) or p-type Alz1Ga1-z1N (0?z1<1) and has a first surface, a second surface, and a third surface. The second layer includes Alx2Ga1-x2N (0?x2<1 and x2<x1) and includes a first partial region, a second partial region, and a third partial region. The third layer includes Alx3Ga1-x3N (0<x3<1 and x2<x3) and includes a fourth partial region, a fifth partial region, and a sixth partial region.
    Type: Application
    Filed: March 20, 2019
    Publication date: July 11, 2019
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Jumpei TAJIMA, Toshiki HIKOSAKA, Kenjiro UESUGI, Shigeya KIMURA, Masahiko KURAGUCHI, Shinya NUNOUE
  • Patent number: 10336377
    Abstract: A work vehicle including: a vehicle body frame; a prime mover part located on a front or rear part of the vehicle body frame; a bonnet configured to open and close by swinging, and covering the prime mover part; and an assist unit configured to assist the bonnet to operate to open. A lateral end portion of the vehicle body frame is provided with a first linkage part with which the assist unit is linked. A lateral end portion of a lower end part of the bonnet, which is located closer to an end cover than the first linkage part is, is provided with a second linkage part with which the assist unit is linked. The assist unit is provided with an expansion/contraction mechanism biased so as to expand, and is located laterally outside the prime mover part and spans the first linkage part and the second linkage part.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: July 2, 2019
    Assignee: Kubota Corporation
    Inventors: Takeshi Komorida, Koichiro Matsumoto, Masaki Takaoka, Arisa Kimura, Tasuku Teraoka, Azusa Furihata, Tomohisa Yamamoto, Toshiki Kanai, Nobuyuki Yamashita, Masayuki Akita, Takashi Kumashiro, Ryo Matsumoto, Hiroki Nagai, Tatsuki Kago, Akihito Mihara
  • Patent number: 10307869
    Abstract: The present invention provides an aluminum alloy brazing sheet for electric resistance welding, which has high strength while being thinned and can reduce the occurrence of welding defects in the electric resistance welding. Disclosed is an aluminum alloy brazing sheet for electric resistance welding, including a core layer and a brazing filler layer cladded on at least one surface of the core layer, wherein the brazing filler layer is made of an aluminum alloy comprising Si: 5.5 to 12.0% by mass, and at least one of Na: 0.0003 to 0.0030% by mass and Sr: 0.0020 to 0.1000% by mass, with the balance being Al and inevitable impurities, wherein the brazing filler layer in a molten state at 650° C. exhibits a viscosity of 0.01 Pa·s or less.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 4, 2019
    Assignee: Kobe Steel, Ltd.
    Inventors: Shimpei Kimura, Toshiki Ueda, Takahiro Izumi, Yuji Shibuya
  • Patent number: D703697
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: April 29, 2014
    Assignee: Panasonic Corporation
    Inventors: Ryuta Onoue, Toshiki Kimura
  • Patent number: D705266
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: May 20, 2014
    Assignee: Panasonic Corporation
    Inventors: Masao Yoshikawa, Toshiki Kimura