Abstract: According to the embodiments, standard cells are arranged in an array in a semiconductor device. In the standard cell, a first diffusion area with a plurality of transistors formed in a main surface region of a semiconductor substrate is formed in a region sandwiched between two power supply lines arranged on the semiconductor substrate. Further, the standard cell includes a potential supplying unit. The potential supplying unit is formed in the main surface region of the semiconductor substrate by a diffusion layer of the same conductive type as that of the first diffusion area and is electrically connected directly to the diffusion area through a contact from the lower portion of the power supply line, to supply a potential from the power supply line to the first diffusion area.

Abstract: A plurality of terminals is formed in a basic cell. One terminal has first to fifth patterns. The first and second patterns are arranged to be spaced from each other. The third and fourth patterns are arranged to be spaced from each other, and are arranged so as to be adjacent to the first and second patterns. The fifth pattern is arranged between the first and second grid lines to interconnect the first to fourth patterns. A dimension of the fifth pattern in a direction of extension of a plurality of grid lines is set to be smaller than a dimension obtained by adding dimensions of the first and second patterns in the direction of extension of the grid lines to an interval of the both patterns, and a dimension obtained by adding dimensions of the third and fourth patterns to an interval of the both patterns.

Abstract: A basic cell placed in a semiconductor device comprises a via contact placed on a wiring grid having a pitch narrower than a pitch between a contact placed in a source region and a contact placed in a drain region of a transistor in a basic cell, and a wiring layer connected to the via contact, being used as a source terminal, a drain terminal, and a gate terminal of the transistor.

Abstract: A plurality of terminals is formed in a basic cell. One terminal has first to fifth patterns. The first and second patterns are arranged to be spaced from each other. The third and fourth patterns are arranged to be spaced from each other, and are arranged so as to be adjacent to the first and second patterns. The fifth pattern is arranged between the first and second grid lines to interconnect the first to fourth patterns. A dimension of the fifth pattern in a direction of extension of a plurality of grid lines is set to be smaller than a dimension obtained by adding dimensions of the first and second patterns in the direction of extension of the grid lines to an interval of the both patterns, and a dimension obtained by adding dimensions of the third and fourth patterns to an interval of the both patterns.

Abstract: A flip-flop circuit includes first and second logic gates, a first selection circuit and a latch circuit. The first logic gate executes a logic operation on a first data signal and a first control signal. The second logic gate executes a logic operation on a second data signal and the first control signal. The operation results of the first and second logic gates are forcibly fixed to a predetermined value irrespective of the first and second data signals, if the first control signal is asserted. A first selection circuit selects one of the operation results of the first and second logic gates, and outputs the selected operation result as a first selection signal. A latch circuit latches the first selection signal.

Abstract: A basic cell placed in a semiconductor device comprises a via contact placed on a wiring grid having a pitch narrower than a pitch between a contact placed in a source region and a contact placed in a drain region of a transistor in a basic cell, and a wiring layer connected to the via contact, being used as a source terminal, a drain terminal, and a gate terminal of the transistor.

Abstract: A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.

Abstract: A first cell block in which a plurality of standard cells with a large cell height are arranged and a second cell block in which a plurality of standard cells with a small cell height are arranged. In the second cell block, transistors are formed whose shape and characteristics are practically the same as those of the transistors provided in the standard cells with the large cell height arranged in the first cell block.

Abstract: A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.

Abstract: A first cell block in which a plurality of standard cells with a large cell height are arranged and a second cell block in which a plurality of standard cells with a small cell height are arranged. In the second cell block, transistors are formed whose shape and characteristics are practically the same as those of the transistors provided in the standard cells with the large cell height arranged in the first cell block.

Abstract: A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.

Abstract: A flip-flop circuit includes first and second logic gates, a first selection circuit and a latch circuit. The first logic gate executes a logic operation on a first data signal and a first control signal. The second logic gate executes a logic operation on a second data signal and the first control signal. The operation results of the first and second logic gates are forcibly fixed to a predetermined value irrespective of the first and second data signals, if the first control signal is asserted. A first selection circuit selects one of the operation results of the first and second logic gates, and outputs the selected operation result as a first selection signal. A latch circuit latches the first selection signal.

Abstract: The present invention provides a standard cell which can reduce an effective cell size and improve an integration degree of a semiconductor integrated circuit. The standard cell includes a plurality of MOS transistors formed on a semiconductor substrate. Then, a plurality of standard cells are adjacent to each other in upper, lower, left and right directions, and constitute the semiconductor integrated circuit. The present invention is intended to reduce the effective cell size in such a way that a source region of a MOS transistor connected to a power supply voltage or a ground voltage is shared between cells adjacent to each other. Also, even if the source region is not shared, a source region of one cell in the cells adjacent to each other is arranged in an empty space region of the other cell in such a way that it bestrides between the cells adjacent to each other.

Abstract: A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.

Abstract: A semiconductor integrated circuit (IC) comprises a functional block which includes a plurality or first and second power source wiring layers arranged parallel to one another and formed so as to extend in a predetermined direction. A plurality of element regions are located between adjacent pairs of the first and second power source wiring layers. A cell block on the (IC) includes a plurality of cell column areas each having third and fourth power source wiring layers which are arranged parallel to each other and formed so as to extend in the predetermined direction. An element region is located between the third and fourth power source wiring layers. A plurality of wiring regions are located between adjacent cell column areas.

Abstract: A semiconductor integrated circuit device is disclosed which comprises a plurality of cell rows each including a plurality of standard cells, signal connection cells provided one at each of the cell rows and located on one straight line across that cell row array, a line for connection cells which is connected to the signal connection cell and adapted to supply a signal which is propagated via the signal connection cell to the cell in the corresponding cell row, and cell-to-cell connection lines each connecting the signal connection cells together and having a broader connection width than that of an ordinary connection line. In the semiconductor integrated circuit device of the present invention the respective signal connection cells are connected together by the cell-to-cell connection line having a broader connection width than that of the ordinary connection line, so that a signal is propagated to the respective cell row in a low-resistance way.

Abstract: The encasing apparatus of this invention comprises a feed mechanism, a turnabout mechanism, and a slide mechanism, and may be additionally provided with a partition sheet feeder depending upon the type of articles to be packed. The turnabout mechanism receives articles delivered from the feed mechanism with a tray, allows each prescribed number of such articles to line up successively in a first direction of the tray so that the articles lie in the same direction, and, after turning the tray around a vertical shaft through a fixed angle, inclines the tray to move the articles in a second direction at an angle of 90.degree. to the first direction, thereby delivering the articles to the slide mechanism. Subsequently, the slide mechanism lines up the articles so as to true up the ends of the articles in the second direction, and then introduces them regularly into the packing box.

Abstract: An automatic working method of castings which comprises the steps of operating a die-casting machine to produce castings; operating a press to trim the castings; operating an industrial robot for carrying the castings from the die-casting machine to the press; operating an incasing device for successively supplying empty boxes to receive the castings; detecting the position of a casting set in the press; removing the casting from the press, in case the casting is improperly set; counting a number of castings delivered to the incasing device, and where the counted number is found to be smaller than a prescribed value, causing a deficient number of castings to be supplied to the incasing device; examining the operation of the machines undertaking the respective steps by a checking device attached to said machines; and, in case the operation of any of the machines is found to be defective, stopping said faulty machine.