Patents by Inventor Toshimasa Yamamoto

Toshimasa Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10020390
    Abstract: A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: July 10, 2018
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun Saito, Hirokazu Fujiwara, Tomoharu Ikeda, Yukihiko Watanabe, Toshimasa Yamamoto
  • Patent number: 9911803
    Abstract: A semiconductor device includes a semiconductor substrate. The element region of the semiconductor substrate includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and a plurality of first floating regions, each the first floating regions having the first conductivity type. The termination region includes a second drift region having the second conductivity type, and a plurality of second floating regions, each of the second floating regions having the first conductivity type. The each of the second floating regions is surrounded by the second drift region. When a depth of a center of the first drift region is taken as a reference depth, at least one of the second floating regions is placed closer to the reference depth than each of the first floating regions.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: March 6, 2018
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun Saito, Sachiko Aoi, Yukihiko Watanabe, Toshimasa Yamamoto
  • Patent number: 9853139
    Abstract: A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided in the front surface in a range outside the second region; a lower end p-type region of the p-type being in contact with a lower end of the termination trench; a lateral p-type region of the p-type being in contact with a lateral surface of the termination trench on an outer circumferential side, connected to the lower end p-type region, and exposed on the front surface; and a plurality of guard ring regions provided on the outer circumferential side with respect to the lateral p-type region and exposed on the front surface.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: December 26, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi Takaya, Jun Saito, Akitaka Soeno, Toshimasa Yamamoto, Narumasa Soejima
  • Patent number: 9853141
    Abstract: Higher voltage resistance is accomplished by expanding a depletion layer more quickly within a circumferential region. A semiconductor device includes an element region, in which an insulated gate type switching element is provided, and the circumferential region. A first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region. Insulating films are provided in the first trench and the second trench. A fourth region of the second conductivity type is provided so as to extend from a bottom surface of the first trench to a bottom surface of the second trench. A fifth region of the first conductivity type continuous from the third region is provided under the fourth region.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: December 26, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun Saito, Hirokazu Fujiwara, Tomoharu Ikeda, Yukihiko Watanabe, Toshimasa Yamamoto
  • Patent number: 9793376
    Abstract: In a method of manufacturing a silicon carbide semiconductor device including a vertical switching element having a trench gate structure, with the use of a substrate having an off angle with respect to a (0001) plane or a (000-1) plane, a trench is formed from a surface of a source region to a depth reaching a drift layer through a base region so that a side wall surface of the trench faces a (11-20) plane or a (1-100) plane, and a gate oxide film is formed without performing sacrificial oxidation after formation of the trench.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: October 17, 2017
    Assignees: DENSO CORPORATION, TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Shinichiro Miyahara, Toshimasa Yamamoto, Jun Morimoto, Narumasa Soejima, Yukihiko Watanabe
  • Patent number: 9780205
    Abstract: A technique disclosed herein improves a voltage resistance of an insulated gate type semiconductor device. A provided method is a method for manufacturing an insulated gate type switching device configured to switch between a front surface electrode and a rear surface electrode. The method includes implanting a first kind of second conductivity type impurities to bottom surfaces of gate trenches and diffusing the implanted first kind of second conductivity type impurities, and implanting a second kind of second conductivity type impurities to the bottom surfaces of the circumferential trenches and diffusing the implanted second kind of second conductivity type impurities.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: October 3, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun Saito, Hirokazu Fujiwara, Tomoharu Ikeda, Yukihiko Watanabe, Toshimasa Yamamoto
  • Patent number: 9755042
    Abstract: An insulated gate semiconductor device provided herein includes a front electrode and a rear electrode and is configured to switch a conducting path between the front electrode and the rear electrode. The insulated gate semiconductor device includes a first circumferential trench provided in the front surface; a second circumferential trend provided in the front surface and deeper than the first circumferential trench; a fifth region of a second conductivity type exposed on a bottom surface of the first circumferential trench; a sixth region of the second conductivity type exposed on a bottom surface of the second circumferential trench; and a seventh region of a first conductivity type connected to the third region and separating the fifth region from the sixth region. A front side end portion of the sixth region being located on a rear side with respect to a rear side end portion of the fifth region.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: September 5, 2017
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun Saito, Tomoharu Ikeda, Tomoyuki Shoji, Toshimasa Yamamoto
  • Patent number: 9627248
    Abstract: An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches.
    Type: Grant
    Filed: February 5, 2015
    Date of Patent: April 18, 2017
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun Saito, Kimimori Hamada, Akitaka Soeno, Hidefumi Takaya, Sachiko Aoi, Toshimasa Yamamoto
  • Publication number: 20170040446
    Abstract: Higher voltage resistance is accomplished by expanding a depletion layer more quickly within a circumferential region. A semiconductor device includes an element region, in which an insulated gate type switching element is provided, and the circumferential region. A first trench and a second trench spaced apart from the first trench are provided in the front surface in the circumferential region. Insulating films are provided in the first trench and the second trench. A fourth region of the second conductivity type is provided so as to extend from a bottom surface of the first trench to a bottom surface of the second trench. A fifth region of the first conductivity type continuous from the third region is provided under the fourth region.
    Type: Application
    Filed: August 4, 2014
    Publication date: February 9, 2017
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun SAITO, Hirokazu FUJIWARA, Tomoharu IKEDA, Yukihiko WATANABE, Toshimasa YAMAMOTO
  • Publication number: 20170025516
    Abstract: An insulated gate semiconductor device provided herein includes a front electrode and a rear electrode and is configured to switch a conducting path between the front electrode and the rear electrode. The insulated gate semiconductor device includes a first circumferential trench provided in the front surface; a second circumferential trend provided in the front surface and deeper than the first circumferential trench; a fifth region of a second conductivity type exposed on a bottom surface of the first circumferential trench; a sixth region of the second conductivity type exposed on a bottom surface of the second circumferential trench; and a seventh region of a first conductivity type connected to the third region and separating the fifth region from the sixth region. A front side end portion of the sixth region being located on a rear side with respect to a rear side end portion of the fifth region.
    Type: Application
    Filed: February 10, 2015
    Publication date: January 26, 2017
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun SAITO, Tomoharu IKEDA, Tomoyuki SHOJI, Toshimasa YAMAMOTO
  • Publication number: 20170018643
    Abstract: A semiconductor device provided herein includes: a fourth region of a p-type being in contact with a lower end of the gate trench; a termination trench provided in the front surface in a range outside the second region; a lower end p-type region of the p-type being in contact with a lower end of the termination trench; a lateral p-type region of the p-type being in contact with a lateral surface of the termination trench on an outer circumferential side, connected to the lower end p-type region, and exposed on the front surface; and a plurality of guard ring regions provided on the outer circumferential side with respect to the lateral p-type region and exposed on the front surface.
    Type: Application
    Filed: February 10, 2015
    Publication date: January 19, 2017
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Hidefumi TAKAYA, Jun SAITO, Akitaka SOENO, Toshimasa YAMAMOTO, Narumasa SOEJIMA
  • Publication number: 20170012121
    Abstract: A technique achieving a higher voltage resistance by a depletion layer extending quickly within a circumferential region is provided. A semiconductor device includes an element region in which an insulated gate type switching element is provided and a circumferential region adjacent to the element region. First and second trenches are provided in the circumferential region. A front surface region of the second-conductivity-type is provided between the first and second trenches. First and second bottom surface regions of the second-conductivity-type are provided in bottom surface ranges of the first and second trenches. First and second side surface regions of the second-conductivity-type connecting the front surface region and the first or second bottom surface region is provided along side surfaces of the first and second trenches. Low area density regions are provided in at least parts of the first and second side surface regions.
    Type: Application
    Filed: August 4, 2014
    Publication date: January 12, 2017
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun SAITO, Hirokazu FUJIWARA, Tomoharu IKEDA, Yukihiko WATANABE, Toshimasa YAMAMOTO
  • Publication number: 20170011952
    Abstract: An insulating gate type semiconductor device being capable of easily depleting an outer periphery region is provided. The insulating gate type semiconductor device includes: first to fourth outer periphery trenches formed in a front surface of a semiconductor substrate; insulating layers located in the outer periphery trenches; fifth semiconductor regions being of a second conductive type and formed in ranges exposed to bottom surfaces of the outer periphery trenches; and a connection region connecting the fifth semiconductor region exposed to the bottom surface of the second outer periphery trench to the fifth semiconductor region exposed to the bottom surface of the third outer periphery trench. A clearance between the second and third outer periphery trenches is wider than each of a clearance between the first and second outer periphery trenches and a clearance between the third and fourth outer periphery trenches.
    Type: Application
    Filed: February 5, 2015
    Publication date: January 12, 2017
    Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Jun SAITO, Kimimori HAMADA, Akitaka SOENO, Hidefumi TAKAYA, Sachiko AOI, Toshimasa YAMAMOTO
  • Publication number: 20160329422
    Abstract: A technique disclosed herein improves a voltage resistance of an insulated gate type semiconductor device. A provided method is a method for manufacturing an insulated gate type switching device configured to switch between a front surface electrode and a rear surface electrode. The method includes implanting a first kind of second conductivity type impurities to bottom surfaces of gate trenches and diffusing the implanted first kind of second conductivity type impurities, and implanting a second kind of second conductivity type impurities to the bottom surfaces of the circumferential trenches and diffusing the implanted second kind of second conductivity type impurities.
    Type: Application
    Filed: August 4, 2014
    Publication date: November 10, 2016
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun SAITO, Hirokazu FUJIWARA, Tomoharu IKEDA, Yukihiko WATANABE, Toshimasa YAMAMOTO
  • Patent number: 9403561
    Abstract: A mounting structure of a sheet metal panel including mounting brackets which are mounted on a peripheral edge portion of a glass-mounting opening formed on a rear-side panel of a cab, and after tentatively holding the sheet metal panel, a peripheral edge of the sheet metal panel is adhered to the rear-side panel in a periphery of the glass-mounting opening, wherein an inclined surface protruding toward a rear of the cab is provided to the rear-side panel along the glass-mounting opening, and the peripheral edge of the sheet metal panel is bent along the inclined surface and extended in the inclined surface direction to make clearance between the peripheral edge and the inclined surface gradually narrowed, to provide an adhesive reservoir between the sheet metal panel and the rear-side panel, and the peripheral edge of the sheet metal panel is in close contact with the inclined surface thereby sealing therebetween.
    Type: Grant
    Filed: May 29, 2013
    Date of Patent: August 2, 2016
    Assignee: VOLVO TRUCKS CORPORATION
    Inventors: Takehiro Saito, Takaichi Arai, Toshimasa Yamamoto
  • Publication number: 20160211319
    Abstract: A semiconductor device includes a semiconductor substrate. The element region of the semiconductor substrate includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and a plurality of first floating regions, each the first floating regions having the first conductivity type. The termination region includes a second drift region having the second conductivity type, and a plurality of second floating regions, each of the second floating regions having the first conductivity type. The each of the second floating regions is surrounded by the second drift region. When a depth of a center of the first drift region is taken as a reference depth, at least one of the second floating regions is placed closer to the reference depth than each of the first floating regions.
    Type: Application
    Filed: September 22, 2014
    Publication date: July 21, 2016
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun SAITO, Sachiko AOI, Yukihiko WATANABE, Toshimasa YAMAMOTO
  • Patent number: 9219142
    Abstract: A semiconductor device includes a semiconductor substrate having an element region and a termination region. The element region includes a first body region having a first conductivity type, a first drift region having a second conductivity type, and first floating regions having the first conductivity type. The termination region includes FLR regions, a second drift region and second floating regions. The FLR regions have the first conductivity type and surrounds the element region. The second drift region has the second conductivity type, makes contact with and surrounds the FLR regions. The second floating regions have the first conductivity type and is surrounded by the second drift region. The second floating regions surround the element region. At least one of the second floating regions is placed at an element region side relative to the closest one of the FLR regions to the element region.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: December 22, 2015
    Assignees: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Jun Saito, Sachiko Aoi, Yukihiko Watanabe, Toshimasa Yamamoto
  • Publication number: 20150298746
    Abstract: A mounting structure of a sheet metal panel including mounting brackets which are mounted on a peripheral edge portion of a glass-mounting opening formed on a rear-side panel of a cab, and after tentatively holding the sheet metal panel, a peripheral edge of the sheet metal panel is adhered to the rear-side panel in a periphery of the glass-mounting opening, wherein an inclined surface protruding toward a rear of the cab is provided to the rear-side panel along the glass-mounting opening, and the peripheral edge of the sheet metal panel is bent along the inclined surface and extended in the inclined surface direction to make clearance between the peripheral edge and the inclined surface gradually narrowed, to provide an adhesive reservoir between the sheet metal panel and the rear-side panel, and the peripheral edge of the sheet metal panel is in close contact with the inclined surface thereby sealing therebetween.
    Type: Application
    Filed: May 29, 2013
    Publication date: October 22, 2015
    Applicant: VOLVO TRUCKS CORPORATION
    Inventors: Takehiro SAITO, Takaichi ARAI, Toshimasa YAMAMOTO
  • Publication number: 20150236127
    Abstract: In a method of manufacturing a silicon carbide semiconductor device including a vertical switching element having a trench gate structure, with the use of a substrate having an off angle with respect to a (0001) plane or a (000-1) plane, a trench is formed from a surface of a source region to a depth reaching a drift layer through a base region so that a side wall surface of the trench faces a (11-20) plane or a (1-100) plane, and a gate oxide film is formed without performing sacrificial oxidation after formation of the trench.
    Type: Application
    Filed: August 6, 2013
    Publication date: August 20, 2015
    Applicants: TOYOTA JIDOSHA KABUSHIKI KAISHA, DENSO CORPORATION
    Inventors: Shinichiro Miyahara, Toshimasa Yamamoto, Jun Morimoto, Narumasa Soejima, Yukihiko Watanabe
  • Patent number: 9029871
    Abstract: A semiconductor device includes a first semiconductor layer surrounding a bottom of the trench gate, a second semiconductor layer disposed along one of end portions of the trench gate in a longitudinal direction of the trench gate, one of end portions of the second semiconductor layer contacting the body layer and the other of the end portions of the second semiconductor layer contacting the first semiconductor layer, and a connecting layer, one of end portions of the connecting layer being connected to the body layer and the other of the end portions of the connecting layer being connected to the first semiconductor layer, the connecting layer contacting the second semiconductor layer, and the connecting layer being separated from the one of the end portions of the trench gate in the longitudinal direction of the trench gate by the second semiconductor layer.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: May 12, 2015
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Akitaka Soeno, Toshimasa Yamamoto