Patents by Inventor Toshinori Shinki

Toshinori Shinki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7844433
    Abstract: A system for designing a utility facility includes a state analyzer analyzing operational states of tools included in a production line, an extraction module extracting an operational period and a standby period of each of the tools, a calculator calculating changes in a quantity of utilities consumed by the tools in operation and in standby, based on the operational periods and the standby periods, and a facility design module designing at least any of a utility facility for supplying utilities to the tools and a utility facility for disposing of utilities discharged from the tools.
    Type: Grant
    Filed: August 28, 2006
    Date of Patent: November 30, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshikatsu Masuda, Toshinori Shinki, Shuichi Samata, Yuuichi Mikata
  • Publication number: 20070061049
    Abstract: A system for designing a utility facility includes a state analyzer analyzing operational states of tools included in a production line, an extraction module extracting an operational period and a standby period of each of the tools, a calculator calculating changes in a quantity of utilities consumed by the tools in operation and in standby, based on the operational periods and the standby periods, and a facility design module designing at least any of a utility facility for supplying utilities to the tools and a utility facility for disposing of utilities discharged from the tools.
    Type: Application
    Filed: August 28, 2006
    Publication date: March 15, 2007
    Inventors: Toshikatsu Masuda, Toshinori Shinki, Shuichi Samata, Yuuichi Mikata
  • Patent number: 4937652
    Abstract: A semiconductor device and a method of manufacturing the same wherein first and second wirings with an interlayer insulating film interposed therebetween are connected through a contact hole formed in the interlayer insulating film. In the semiconductor device, the first and second wirings are connected via a low resistive, conductive metal layer obtained by reducing a highly resistive oxide layer with a highly oxidizing metal, the highly resistive oxide layer being exposed within the contact hole on the surface of the first wiring. In the method of manufacturing a semiconductor device, a contact hole is opened in the interlayer insulation on the first wiring, a highly oxidizing metal is deposited on the highly resistive oxide layer on the surface of the first wiring within the contact hole, and the highly resistive oxide layer is reduced with the highly oxidizing metal to change the highly resistive oxide layer to a low resistive, conductive metal layer.
    Type: Grant
    Filed: September 30, 1988
    Date of Patent: June 26, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuya Okumura, Toshinori Shinki, Toshiaki Idaka, Riichirou Aoki
  • Patent number: 4502210
    Abstract: A semiconductor device is manufactured by selectively removing an insulating film which covers at least one conductive layer to form at least one contact hole partially exposing the conductive layer. Then, a layer of an inorganic conductive material having a melting point lower than the material comprising the conductive layer is formed on a surface of the insulating film and is melted to fill the contact hole with the inorganic conductive material. Finally a wiring layer is formed in contact with the inorganic conductive material filled in the contact hole.
    Type: Grant
    Filed: June 8, 1983
    Date of Patent: March 5, 1985
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Katsuya Okumura, Toshinori Shinki, Takashi Sato, Masaaki Ueda