Patents by Inventor Toshio Fujisawa

Toshio Fujisawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240100728
    Abstract: A recording medium processing apparatus includes: a pressing unit that presses one surface of a transported recording medium against a to-be-pressed section; and a cutting unit that cuts the recording medium pressed against the to-be-pressed section.
    Type: Application
    Filed: March 23, 2023
    Publication date: March 28, 2024
    Applicant: FUJIFILM Business Innovation Corp.
    Inventors: Hiroaki MOGI, Shiro Ohashi, Eiichiro Tokuhiro, Toshio Fujisawa
  • Patent number: 11942176
    Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.
    Type: Grant
    Filed: September 15, 2021
    Date of Patent: March 26, 2024
    Assignee: Kioxia Corporation
    Inventors: Tomoya Sanuki, Xu Li, Masayuki Miura, Takayuki Miyazaki, Toshio Fujisawa, Hiroto Nakai, Hideko Mukaida, Mie Matsuo
  • Publication number: 20240086077
    Abstract: According to one embodiment, a memory system includes a nonvolatile semiconductor storage device and a memory controller. The nonvolatile semiconductor storage device includes at least one memory device including a plurality of memory cells corresponding to a plurality of pages. The memory controller is configured to control the nonvolatile semiconductor storage device. The pages include a first page. The memory controller is configured to: read first data stored in the first page from the nonvolatile semiconductor storage device; correct a fail bit included in the read first data; generate first spare data including information on the fail bit corrected in the read first data; and store the first spare data in the nonvolatile semiconductor storage device.
    Type: Application
    Filed: March 10, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Tomoya SANUKI, Toshio FUJISAWA, Keisuke NAKATSUKA
  • Patent number: 11923325
    Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Kioxia Corporation
    Inventors: Yasuhito Yoshimizu, Takashi Fukushima, Tatsuro Hitomi, Arata Inoue, Masayuki Miura, Shinichi Kanno, Toshio Fujisawa, Keisuke Nakatsuka, Tomoya Sanuki
  • Publication number: 20240070062
    Abstract: According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventors: Daisuke IWAI, Toshio FUJISAWA, Keigo HARA
  • Patent number: 11868285
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.
    Type: Grant
    Filed: November 18, 2022
    Date of Patent: January 9, 2024
    Assignee: Kioxia Corporation
    Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
  • Patent number: 11847050
    Abstract: According to one embodiment, a nonvolatile memory includes a memory chip and a command processing unit. The command processing unit stores data read from a first position of the memory chip in a memory when a first command for compaction is received from a controller, transmits validity determination information used for determining whether or not the data read from the first position is valid to the controller, and writes valid data of the data stored in the memory to a second position of the memory chip when a second command for the compaction and validity identification information that identifies the valid data are received from the controller.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: December 19, 2023
    Assignee: Kioxia Corporation
    Inventors: Daisuke Iwai, Toshio Fujisawa, Keigo Hara
  • Patent number: 11756946
    Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.
    Type: Grant
    Filed: June 23, 2022
    Date of Patent: September 12, 2023
    Assignee: Kioxia Corporation
    Inventors: Tomoya Sanuki, Toshio Fujisawa, Hiroshi Maejima, Takashi Maeda
  • Publication number: 20230078983
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.
    Type: Application
    Filed: November 18, 2022
    Publication date: March 16, 2023
    Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
  • Patent number: 11579796
    Abstract: A memory system has a memory, a first substrate on which the memory is mounted and which is set to a temperature of ?40[° C.] or lower, a controller configured to control the memory; and a second substrate on which the controller is mounted, which is set to a temperature of ?40[° C.] or higher, and which transmits and receives a signal to and from the first substrate via a signal transmission cable.
    Type: Grant
    Filed: March 10, 2021
    Date of Patent: February 14, 2023
    Assignee: Kioxia Corporation
    Inventors: Tomoya Sanuki, Yuta Aiba, Hitomi Tanaka, Masayuki Miura, Mie Matsuo, Toshio Fujisawa, Takashi Maeda
  • Publication number: 20230017909
    Abstract: A semiconductor storage device includes a memory cell array and a control circuit. The memory cell array includes a plurality of memory strings, a plurality of word lines, each of which is connected to the memory strings, and a plurality of bit lines connected to the memory strings, respectively. The plurality of bit lines are grouped into a plurality of bit line groups. The control circuit is configured to receive a read command and first address information specifying one or more of the bit line groups. The control circuit is configured to, in response to the read command, read data selectively from each memory string connected to each bit line in the one or more bit line groups specified by the first address information, and output the read data.
    Type: Application
    Filed: February 25, 2022
    Publication date: January 19, 2023
    Inventors: Tomoya SANUKI, Keisuke NAKATSUKA, Daisuke FUJIWARA, Toshio FUJISAWA
  • Patent number: 11537536
    Abstract: According to one embodiment, a memory device includes a nonvolatile memory, a volatile memory, a controller, and a board. The nonvolatile memory stores data. The volatile memory holds a part of the data stored in the nonvolatile memory. The memory controller controls the volatile memory and the nonvolatile memory. The nonvolatile memory, the volatile memory, and the memory controller are provided on the board. The memory controller transmits an interrupt signal to a request source, when the volatile memory does not have any data corresponding to an address which the request source requests to access.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: December 27, 2022
    Assignee: Kioxia Corporation
    Inventors: Toshio Fujisawa, Nobuhiro Kondo, Shoji Sawamura, Kenichi Maeda, Atsushi Kunimatsu
  • Publication number: 20220320065
    Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.
    Type: Application
    Filed: June 23, 2022
    Publication date: October 6, 2022
    Inventors: Tomoya SANUKI, Toshio FUJISAWA, Hiroshi MAEJIMA, Takashi MAEDA
  • Publication number: 20220301599
    Abstract: A semiconductor memory device has a plastic package including an inductor, a first memory chip including a booster circuit that boosts a voltage from a first voltage to a second voltage using the inductor, and a second memory chip having a terminal supplied with the second voltage from the first memory chip.
    Type: Application
    Filed: September 15, 2021
    Publication date: September 22, 2022
    Inventors: Tomoya SANUKI, Xu LI, Masayuki MIURA, Takayuki MIYAZAKI, Toshio FUJISAWA, Hiroto NAKAI, Hideko MUKAIDA, Mie MATSUO
  • Patent number: 11422712
    Abstract: According to one embodiment, a storage device includes a stage on which a semiconductor wafer can be mounted, wherein data is capable of being read from the semiconductor wafer or data is capable of being written to the semiconductor wafer. The storage device further includes a plurality of probe pins for reading or writing data, and a controller connected the probe pins. The semiconductor wafer includes electrodes connectable to the probe pins, a first memory area that can store user data, and a second memory area that can store identification information for identification of the semiconductor wafer and a check code for checking integrity of the identification information. The controller is capable of reading the identification information and the check code from the second memory area.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: August 23, 2022
    Assignee: Kioxia Corporation
    Inventors: Yasuhito Yoshimizu, Takashi Fukushima, Tatsuro Hitomi, Arata Inoue, Masayuki Miura, Shinichi Kanno, Toshio Fujisawa, Keisuke Nakatsuka, Tomoya Sanuki
  • Patent number: 11417642
    Abstract: A semiconductor storage device includes a plurality of memory chips and a circuit chip. The plurality of memory chips and the circuit chip are stacked on each other. Each of the plurality of memory chips has a memory cell array that includes a plurality of memory cells. The circuit chip includes a data latch configured to store page data for writing or reading data into or from the memory cell array of each of the memory chips.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: August 16, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Tomoya Sanuki, Toshio Fujisawa, Hiroshi Maejima, Takashi Maeda
  • Publication number: 20220223552
    Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.
    Type: Application
    Filed: March 15, 2022
    Publication date: July 14, 2022
    Inventors: Yasuhito YOSHIMIZU, Takashi FUKUSHIMA, Tatsuro HITOMI, Arata INOUE, Masayuki MIURA, Shinichi KANNO, Toshio FUJISAWA, Keisuke NAKATSUKA, Tomoya SANUKI
  • Publication number: 20220204270
    Abstract: According to one embodiment, a storage device includes a control apparatus and a stocker. The control apparatus writes data to or reads data from a storage medium that includes a plurality of non-volatile memory chips. The stocker stores a plurality of the storage media that are detached from the control apparatus. The control apparatus includes a first temperature control system. The first temperature control system raises temperature of the storage medium to a first temperature or higher. The stocker includes a second temperature control system. The second temperature control system cools the storage medium to a second temperature or lower. The second temperature is lower than the first temperature.
    Type: Application
    Filed: March 14, 2022
    Publication date: June 30, 2022
    Inventors: Yasuhito YOSHIMIZU, Takashi FUKUSHIMA, Tatsuro HITOMI, Arata INOUE, Masayuki MIURA, Shinichi KANNO, Toshio FUJISAWA, Keisuke NAKATSUKA, Tomoya SANUKI
  • Publication number: 20220091772
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory with a plurality of blocks. A controller in the system controls the writing of data to the non-volatile semiconductor memory and includes a host I/F control interface to receive write command information including file allocation information indicating a location for write data, a file information management unit to assign an erasure level to a file and output a file identifier in which a file name, a file size, and the erasure level of the file are combined, and a flash translation layer unit to allocate each file on a single file per block basis based on the write command information and the file identifier.
    Type: Application
    Filed: August 24, 2021
    Publication date: March 24, 2022
    Inventors: Toshio FUJISAWA, Tomoya SANUKI, Hitomi TANAKA, Takeshi ISHIHARA, Yasuhito YOSHIMIZU
  • Publication number: 20220083261
    Abstract: A memory system of an embodiment includes a NAND memory and a memory controller. The NAND memory includes an encoder configured to convert first data into second data including a plurality of code words generated by dividing the first data into the code words, generate parity data in a horizontal direction of the second data for error check and correct for each code word and encode the first data, and a decoder. A control circuit of the NAND memory controls the decoder to perform hard decision decoding using the parity data in the horizontal direction on readout target data when a readout command is received and outputs the decoded readout target data to the memory controller when the hard decision decoding of the readout target data is successful.
    Type: Application
    Filed: June 1, 2021
    Publication date: March 17, 2022
    Applicant: Kioxia Corporation
    Inventors: Daisuke FUJIWARA, Tomoya SANUKI, Toshio FUJISAWA