Patents by Inventor Toshio Hasegawa
Toshio Hasegawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9101067Abstract: In a Cu wiring forming method for forming a Cu wiring by filling Cu in a recess which is formed in a substrate in a predetermined pattern, a barrier film formed of a TaAlN film is formed at least on the surface of the recess by thermal ALD or thermal CVD. Then a Cu film is formed to fill the recess with the Cu film. Further, the Cu wiring is formed in the recess by polishing the entire surface of the substrate by CMP.Type: GrantFiled: December 20, 2013Date of Patent: August 4, 2015Assignee: TOKYO ELECTRON LIMITEDInventors: Tadahiro Ishizaka, Toshio Hasegawa
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Publication number: 20150132939Abstract: A method is provided for forming a semiconductor device. According to one embodiment, the method includes providing a substrate having a Ge-containing film thereon, identifying a first plasma processing recipe that uses a metal chloride precursor to deposit a first metal layer on the Ge-containing film at a higher rate than the Ge-containing film is etched by the metal chloride precursor, identifying a second plasma processing recipe that uses the metal chloride precursor to etch the Ge-containing film at a higher rate than a second metal layer is deposited on the Ge-containing film by the metal chloride precursor, performing the first plasma processing recipe to deposit the first metal layer on the Ge-containing film, and performing the second plasma processing recipe to deposit the second metal layer on the first metal layer, and where the second metal layer is deposited at a higher rate than the first metal layer.Type: ApplicationFiled: November 6, 2014Publication date: May 14, 2015Inventors: Toshio Hasegawa, Hideaki Yamasaki
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Patent number: 8846474Abstract: Embodiments of the invention provide dual workfunction semiconductor devices and methods for manufacturing thereof. According to one embodiment, the method includes providing a substrate containing first and second device regions, depositing a dielectric film on the substrate, and forming a first metal-containing gate electrode film on the dielectric film, wherein a thickness of the first metal-containing gate electrode film is less over the first device region than over the second device region. The method further includes depositing a second metal-containing gate electrode film on the first metal-containing gate electrode film, patterning the second metal-containing gate electrode film, the first metal-containing gate electrode film, and the dielectric film to form a first gate stack above the first device region and a second gate stack above the second device region.Type: GrantFiled: September 30, 2012Date of Patent: September 30, 2014Assignee: Tokyo Electron LimitedInventors: Genji Nakamura, Toshio Hasegawa
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Patent number: 8785310Abstract: A method is provided for forming a metal silicide layer on a substrate. According to one embodiment the method includes providing the substrate in a process chamber, exposing the substrate at a first substrate temperature to a plasma generated from a deposition gas containing a metal precursor, where the plasma exposure forms a conformal metal-containing layer on the substrate in a self-limiting process. The method further includes exposing the metal-containing layer at a second substrate temperature to a reducing gas in the absence of a plasma, where the exposing steps are alternatively performed at least once to form the metal silicide layer, and the deposition gas does not contain the reducing gas. The method provides conformal metal silicide formation in deep trenches with high aspect ratios.Type: GrantFiled: March 22, 2012Date of Patent: July 22, 2014Assignee: Tokyo Electron LimitedInventors: Toshio Hasegawa, Kunihiro Tada, Hideaki Yamasaki, David L. O'Meara, Gerrit J. Leusink
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Publication number: 20140175046Abstract: In a Cu wiring forming method for forming a Cu wiring by filling Cu in a recess which is formed in a substrate in a predetermined pattern, a barrier film formed of a TaAlN film is formed at least on the surface of the recess by thermal ALD or thermal CVD. Then a Cu film is formed to fill the recess with the Cu film. Further, the Cu wiring is formed in the recess by polishing the entire surface of the substrate by CMP.Type: ApplicationFiled: December 20, 2013Publication date: June 26, 2014Applicant: Tokyo Electron LimitedInventors: Tadahiro ISHIZAKA, Toshio HASEGAWA
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Publication number: 20140048885Abstract: Embodiments of the invention provide dual workfunction semiconductor devices and methods for manufacturing thereof. According to one embodiment, the method includes providing a substrate containing first and second device regions, depositing a dielectric film on the substrate, and forming a first metal-containing gate electrode film on the dielectric film, wherein a thickness of the first metal-containing gate electrode film is less over the first device region than over the second device region. The method further includes depositing a second metal-containing gate electrode film on the first metal-containing gate electrode film, patterning the second metal-containing gate electrode film, the first metal-containing gate electrode film, and the dielectric film to form a first gate stack above the first device region and a second gate stack above the second device region.Type: ApplicationFiled: September 30, 2012Publication date: February 20, 2014Applicant: TOKYO ELECTRON LIMITEDInventors: Genji Nakamura, Toshio Hasegawa
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Publication number: 20130196505Abstract: A method is provided for forming a metal silicide layer on a substrate. According to one embodiment the method includes providing the substrate in a process chamber, exposing the substrate at a first substrate temperature to a plasma generated from a deposition gas containing a metal precursor, where the plasma exposure forms a conformal metal-containing layer on the substrate in a self-limiting process. The method further includes exposing the metal-containing layer at a second substrate temperature to a reducing gas in the absence of a plasma, where the exposing steps are alternatively performed at least once to form the metal silicide layer, and the deposition gas does not contain the reducing gas. The method provides conformal metal silicide formation in deep trenches with high aspect ratios.Type: ApplicationFiled: March 22, 2012Publication date: August 1, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Toshio Hasegawa, Kunihiro Tada, Hideaki Yamasaki, David L. O'Meara, Gerrit J. Leusink
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Publication number: 20130149852Abstract: A method for forming a semiconductor device includes providing in a process chamber a metal-containing gate electrode film on a substrate, flowing a process gas consisting of hydrogen (H2) and optionally a noble gas into the process chamber, forming plasma excited species from the process gas by a microwave plasma source, and exposing the metal-containing gate electrode film to the plasma excited species to form a modified metal-containing gate electrode film having a lower work function than the metal-containing gate electrode film. Other embodiments describe forming semiconductor devices with gate stacks containing modified metal-containing gate electrodes for NMOS and PMOS transistors.Type: ApplicationFiled: December 8, 2011Publication date: June 13, 2013Applicant: TOKYO ELECTRON LIMITEDInventors: Genji Nakamura, Toshio Hasegawa
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Patent number: 8389053Abstract: A method of cleaning a powdery source supply system prevents outflow of particles from a chamber or an introduction line in a film forming process. A substrate processing system includes a powdery source supply system and a film forming processing unit. The powdery source supply system includes an ampoule for accommodating a powdery source, a carrier gas supply unit for supplying a carrier gas into the ampoule, an introduction line for connecting the ampoule and the film forming processing unit, a purge line branched from the introduction line, and a valve for opening or closing the introduction line. When the valve is opened and the interior of the purge line is evacuated prior to the film forming process, the carrier gas supply unit supplies a carrier gas so that the viscous force acting on particles by the carrier gas is greater than the viscous force in the film forming process.Type: GrantFiled: March 26, 2008Date of Patent: March 5, 2013Assignee: Tokyo Electron LimitedInventors: Tsuyoshi Moriya, Toshio Hasegawa, Hideaki Yamasaki
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Patent number: 8270841Abstract: The present invention is directed to realize a stable and highly-efficient quantum communication without being influenced by the jitter of the heralding signal. In regard to the quantum encryption transmitting apparatus 200, the pulse-driven heralded single-photon source 201 generates a photon pair, outputs one photon of the photon pair, and outputs the other photon of the photon pair as a heralding signal. The timing adjuster 202 synchronizes the heralding signal with a clock signal for pulse driving the pulse-driven heralded single-photon source 201, and outputs as a trigger signal. The quantum communication modulating unit 203 implements the signal modulation to a quantum signal, in timing with the trigger signal, and transmits the quantum signal to the quantum encryption receiving apparatus 300 via the quantum communication path 101. The heralding signal transmitting unit 205 transmits the heralding signal to the quantum encryption receiving apparatus 300 via the heralding signal communication path 102.Type: GrantFiled: August 4, 2006Date of Patent: September 18, 2012Assignees: Mitsubishi Electric Corporation, National University Corporation Hokkaido UniversityInventors: Tsuyoshi Nishioka, Shigeki Takeuchi, Alexandre Soujaeff, Toshio Hasegawa, Junnichi Abe
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Patent number: 7989353Abstract: Method for operating a processing system and refurbishing a ceramic substrate holder within a process chamber of the processing system are described. The method includes plasma processing one or more substrates on the ceramic substrate holder, where the processing causes erosion of a nitride material of the ceramic substrate holder. The method further includes refurbishing the ceramic substrate holder in-situ without a substrate residing on the ceramic substrate holder, where the refurbishing includes exposing the ceramic substrate holder to a plasma-excited nitrogen-containing gas in the process chamber to at least partially reverse the erosion of the nitride material.Type: GrantFiled: January 2, 2008Date of Patent: August 2, 2011Assignee: Tokyo Electron LimitedInventors: Tadahiro Ishizaka, Kentaro Asakura, Masanao Ando, Toshio Hasegawa
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Patent number: 7985680Abstract: A method for forming an aluminum-doped metal (tantalum or titanium) carbonitride gate electrode for a semiconductor device is described. The method includes providing a substrate containing a dielectric layer thereon, and forming the gate electrode on the dielectric layer in the absence of plasma. The gate electrode is formed by depositing a metal carbonitride film, and adsorbing an atomic layer of an aluminum precursor on the metal carbonitride film. The steps of depositing and adsorbing may be repeated a desired number of times until the aluminum-doped metal carbonitride gate electrode has a desired thickness.Type: GrantFiled: August 25, 2008Date of Patent: July 26, 2011Assignee: Tokyo Electron LimitedInventors: Toshio Hasegawa, Gerrit J Leusink
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Patent number: 7935384Abstract: The present invention relates to a method of forming a metal-nitride film onto a surface of an object to be processed in a processing container in which a vacuum can be created. The method of the invention includes: a step of continuously supplying an inert gas into a processing container set at a low film-forming temperature; and a step of intermittently supplying a metal-source gas into the processing container, during the step of continuously supplying the inert gas. During the step of intermittently supplying the metal-source gas, a nitrogen-including reduction gas is supplied into the processing container at the same time that the metal-source gas is supplied, during a supply term of the metal-source gas. The nitrogen-including reduction gas is also supplied into the processing container for a term shorter than a non-supply term of the metal-source gas, during the non-supply term of the metal-source gas.Type: GrantFiled: September 2, 2002Date of Patent: May 3, 2011Assignee: Tokyo Electron LimitedInventor: Toshio Hasegawa
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Patent number: 7894604Abstract: Provided is a quantum cryptography communication apparatus capable of preventing a go photon pulse from being phase modulated and also capable of freely selecting any repetitive frequency of a light source.Type: GrantFiled: May 17, 2004Date of Patent: February 22, 2011Assignee: Mitsubishi Electric CorporationInventors: Tsuyoshi Nishioka, Toshio Hasegawa, Hirokazu Ishizuka
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Publication number: 20100226659Abstract: The present invention is directed to realize a stable and highly-efficient quantum communication without being influenced by the jitter of the heralding signal. In regard to the quantum encryption transmitting apparatus 200, the pulse-driven heralded single-photon source 201 generates a photon pair, outputs one photon of the photon pair, and outputs the other photon of the photon pair as a heralding signal. The timing adjuster 202 synchronizes the heralding signal with a clock signal for pulse driving the pulse-driven heralded single-photon source 201, and outputs as a trigger signal. The quantum communication modulating unit 203 implements the signal modulation to a quantum signal, in timing with the trigger signal, and transmits the quantum signal to the quantum encryption receiving apparatus 300 via the quantum communication path 101. The heralding signal transmitting unit 205 transmits the heralding signal to the quantum encryption receiving apparatus 300 via the heralding signal communication path 102.Type: ApplicationFiled: August 4, 2006Publication date: September 9, 2010Applicants: Mitsubishi Electric Corporation, National University Corp. Hokkaido UniversityInventors: Tsuyoshi Nishioka, Shigeki Takeuchi, Alexandre Soujaeff, Toshio Hasegawa, Junnichi Abe
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Patent number: 7776742Abstract: A TiN film is formed to have a predetermined thickness on a semiconductor wafer by heating the semiconductor wafer at a film formation temperature within a process container and performing a cycle including a first step and a second step at least once. The first step is arranged to supply a TiCl4 gas and a NH3 gas to form a film of TiN by CVD. The second step is arranged to stop the TiCl4 gas and supply the NH3 gas. In film formation, the semiconductor wafer is set at a temperature of less than 450° C. and the process container is set to have therein a total pressure of more than 100 Pa. The NH3 gas is set to have a partial pressure of 30 Pa or less within the process container in the first step.Type: GrantFiled: January 14, 2005Date of Patent: August 17, 2010Assignee: Tokyo Electron LimitedInventor: Toshio Hasegawa
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Patent number: 7776733Abstract: Embodiments of the invention describe TiN deposition methods suitable for high volume manufacturing of semiconductor devices on large patterned substrates (wafers). One embodiment describes a chemical vapor deposition (CVD) process using high gas flow rate of a tetrakis(ethylmethylamino) titanium (TEMAT) precursor vapor along with an inert carrier gas at a low process chamber pressure that provides high deposition rate of conformal TiN films with good step coverage in surface reaction limited regime. Other embodiments describe cyclical TiN deposition methods using TEMAT precursor vapor and a nitrogen precursor.Type: GrantFiled: May 2, 2007Date of Patent: August 17, 2010Assignee: Tokyo Electron LimitedInventor: Toshio Hasegawa
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Publication number: 20100136230Abstract: A method of cleaning a powdery source supply system prevents outflow of particles from a chamber or an introduction line in a film forming process. A substrate processing system includes a powdery source supply system and a film forming processing unit. The powdery source supply system includes an ampoule for accommodating a powdery source, a carrier gas supply unit for supplying a carrier gas into the ampoule, an introduction line for connecting the ampoule and the film forming processing unit, a purge line branched from the introduction line, and a valve for opening or closing the introduction line. When the valve is opened and the interior of the purge line is evacuated prior to the film forming process, the carrier gas supply unit supplies a carrier gas so that the viscous force acting on particles by the carrier gas is greater than the viscous force in the film forming process.Type: ApplicationFiled: March 26, 2008Publication date: June 3, 2010Applicant: Tokyo Electron LimitedInventors: Tsuyoshi Moriya, Toshio Hasegawa, Hideaki Yamasaki
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Publication number: 20100048009Abstract: A method for forming an aluminum-doped metal (tantalum or titanium) carbonitride gate electrode for a semiconductor device is described. The method includes providing a substrate containing a dielectric layer thereon, and forming the gate electrode on the dielectric layer in the absence of plasma. The gate electrode is formed by depositing a metal carbonitride film, and adsorbing an atomic layer of an aluminum precursor on the metal carbonitride film. The steps of depositing and adsorbing may be repeated a desired number of times until the aluminum-doped metal carbonitride gate electrode has a desired thickness.Type: ApplicationFiled: August 25, 2008Publication date: February 25, 2010Applicant: TOKYO ELECTRON LIMITEDInventors: Toshio Hasegawa, Gerrit J. Leusink
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Publication number: 20100047472Abstract: The present invention relates to a method of forming a metal-nitride film onto a surface of an object to be processed in a processing container in which a vacuum can be created. The method of the invention includes: a step of continuously supplying an inert gas into a processing container set at a high film-forming temperature; and a step of intermittently supplying a metal-source gas into the processing container, during the step of continuously supplying the inert gas. During the step of intermittently supplying the metal-source gas, a nitrogen-including reduction gas is supplied into the processing container at the same time that the metal-source gas is supplied, during a supply term of the metal-source gas. The nitrogen-including reduction gas is also supplied into the processing container for a term shorter than a non-supply term of the metal-source gas, during the non-supply term of the metal-source gas.Type: ApplicationFiled: October 29, 2009Publication date: February 25, 2010Applicant: TOKYO ELECTRON LIMITEDInventor: Toshio HASEGAWA