Patents by Inventor Toshio Kumamoto
Toshio Kumamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050145987Abstract: A semiconductor device includes a semiconductor substrate including a main surface; a plurality of first interconnections formed in a capacitance forming region defined on the main surface and extending in a predetermined direction; a plurality of second interconnections each adjacent to the first interconnection located at an edge of the capacitance forming region, extending in the predetermined direction, and having a fixed potential; and an insulating layer formed on the main surface and filling in between each of the first interconnections and between the first interconnection and the second interconnection adjacent to each other. The first interconnections and the second interconnections are located at substantially equal intervals in a plane parallel to the main surface, and located to align in a direction substantially perpendicular to the predetermined direction.Type: ApplicationFiled: December 17, 2004Publication date: July 7, 2005Applicants: Renesas Technology Corp., Renesas Device Design Corp.Inventors: Takashi Okuda, Yasuo Morimoto, Yuko Maruyama, Toshio Kumamoto
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Patent number: 6809582Abstract: Two groups of diodes are connected to internal lines transmitting complementary signals, respectively, and positions of the centers of gravity of the groups of diodes are made coincident with each other. A circuit capable of preventing the deviation of the characteristics of differential transistor pair caused by an antenna effect and highly immune against a substrate noise can be achieved.Type: GrantFiled: July 10, 2003Date of Patent: October 26, 2004Assignee: Renesas Technology Corp.Inventors: Yasuo Morimoto, Toshio Kumamoto, Takashi Okuda
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Publication number: 20040189350Abstract: Two groups of diodes are connected to internal lines transmitting complementary signals, respectively, and positions of the centers of gravity of the groups of diodes are made coincident with each other. A circuit capable of preventing the deviation of the characteristics of differential transistor pair caused by an antenna effect and highly immune against a substrate noise can be achieved.Type: ApplicationFiled: July 10, 2003Publication date: September 30, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Yasuo Morimoto, Toshio Kumamoto, Takashi Okuda
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Publication number: 20040183606Abstract: An oscillator circuit is formed of a differential LC resonant circuit formed of an L load differential circuit including inductance-variable portions and a capacitor element, and a positive feedback circuit formed of N-channel MOS transistors. The inductance-variable portion is configured to vary the inductance by selecting a plurality of switch circuits arranged between a plurality of arbitrary positions on a spiral interconnection layer and the input/output terminal, and thereby can control an oscillation frequency. The inductance-variable portions form an inductor pair when the switch circuit among the switch circuits coupled between the first input/output terminals is turned on together with the switch circuit.Type: ApplicationFiled: August 21, 2003Publication date: September 23, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Hiroshi Komurasaki, Tomohiro Sano, Hisayasu Sato, Toshio Kumamoto, Yasushi Hashizume
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Publication number: 20040178937Abstract: A &Dgr;&Sgr; modulator modulates only an error component separated by a component separating portion. Therefore, even if the number of order of the &Dgr;&Sgr; modulator increases, an amplitude of an output of an integrator in the final stage does not excessively increase, and the stability of the modulator can be achieved. Since the signal component separated by the component separating portion does not pass through the &Dgr;&Sgr; modulator, an intensity of an input signal can be maintained as it is, and the modulator can have high precision.Type: ApplicationFiled: November 19, 2003Publication date: September 16, 2004Applicant: RENESAS TECHNOLOGY CORP.Inventors: Takashi Okuda, Toshio Kumamoto, Yasuo Morimoto
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Patent number: 6784548Abstract: A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.Type: GrantFiled: December 4, 2002Date of Patent: August 31, 2004Assignee: Renesas Technology Corp.Inventors: Hiroyuki Kouno, Toshio Kumamoto, Takahiro Miki, Hisayasu Satoh
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Patent number: 6734816Abstract: A D/A converter including a plurality of potential generating sections. They each receive a 1-bit signal from one of an input terminal and delay circuit, and a clock signal or inverted clock signal from an input section or inverter for inverting the clock signal. When the clock signal or inverted clock signal is at a first signal level, they generate a first reference potential or second reference potential in response to the signal level of the 1-bit signal. When the clock signal or inverted clock signal is at the second level, they generate an intermediate potential between the first and second reference potentials. The potentials generated by the plurality of potential generating sections are combined by a combining section. The D/A converter can improve resistance to jitter, and to simplify the configuration of a post-stage filter circuit.Type: GrantFiled: April 8, 2003Date of Patent: May 11, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuo Morimoto, Toshio Kumamoto, Takashi Okuda
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Patent number: 6734814Abstract: In a modulator, an attenuator attenuates an input signal, a delay element gives a delay of 1 sample period to the attenuated signal, an adder subtracts a quantized signal that has been fed back with a delay of 1 sample period, from the delayed signal, two or more integrators integrate a result of the subtraction, an adder which adds outputs of the respective integrators and the attenuated signal, and a quantizer quantizes a result of the addition, outputs a result of the quantization as an output signal and feeds back the output signal to the subtractor.Type: GrantFiled: June 14, 2002Date of Patent: May 11, 2004Assignee: Renesas Technology Corp.Inventors: Takashi Okuda, Toshio Kumamoto, Yasuo Morimoto
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Publication number: 20040061634Abstract: A D/A converter including a plurality of potential generating sections. They each receive a 1-bit signal from one of an input terminal and delay circuit, and a clock signal or inverted clock signal from an input section or inverter for inverting the clock signal. When the clock signal or inverted clock signal is at a first signal level, they generate a first reference potential or second reference potential in response to the signal level of the 1-bit signal. When the clock signal or inverted clock signal is at the second level, they generate an intermediate potential between the first and second reference potentials. The potentials generated by the plurality of potential generating sections are combined by a combining section. The D/A converter can improve resistance to jitter, and to simplify the configuration of a post-stage filter circuit.Type: ApplicationFiled: April 8, 2003Publication date: April 1, 2004Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Yasuo Morimoto, Toshio Kumamoto, Takashi Okuda
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Patent number: 6703957Abstract: When forming PDM pulses by a D/A converter in accordance with digital signals, the D/A converter causes at least one of the rising stage and the falling stage of each of the PDM pulses to change stepwise. In addition, when forming PWM pulses by another D/A converter, the D/A converter causes at least one of the rising stage and the falling stage of each of the PWM pulses to change stepwise.Type: GrantFiled: May 14, 2002Date of Patent: March 9, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Yasuo Morimoto, Toshio Kumamoto, Takashi Okuda, Takahiro Miki
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Publication number: 20030117306Abstract: In a modulator, an attenuator attenuates an input signal, a delay element gives a delay of 1 sample period to the attenuated signal, an adder subtracts a quantized signal that has been fed back with a delay of 1 sample period, from the delayed signal, two or more integrators integrate a result of the subtraction, an adder which adds outputs of the respective integrators and the attenuated signal, and a quantizer quantizes a result of the addition, outputs a result of the quantization as an output signal and feeds back the output signal to the subtractor.Type: ApplicationFiled: June 14, 2002Publication date: June 26, 2003Inventors: Takashi Okuda, Toshio Kumamoto, Yasuo Morimoto
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Patent number: 6573588Abstract: A P well region formed on a buried N well region and a n+ active region that are connected each other through a lead wire, serve as one terminal T1, and a gate electrode and a buried N well region that are connected each other through a leading N well region and a lead wire, serve as the other terminal T2. Thereby, the voltage dependence of capacitance C1 formed between the gate electrode and the n+ active region is canceled out with the voltage dependence of capacitance C2 formed between the P well region and the buried N well region.Type: GrantFiled: October 24, 2002Date of Patent: June 3, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshio Kumamoto, Takashi Okuda, Yasuo Morimoto
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Publication number: 20030071263Abstract: A gate electrode (1) has a relatively long gate length (L) of e.g., about 10 &mgr;m. In a region immediately above the gate electrode (1) which is sandwiched between first-layer metals (1AL; 4, 5) provided is a metal dummy pattern (6) having a width (W:<L) in the first direction (D1) and extending in the second direction (D2) perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern (6) in the second direction (D2) is equal to a geometric center (GC) of the gate electrode (1) in the second direction (D2). This maintains the symmetry in shape of the metal dummy pattern (6) as viewed from the gate electrode (1). Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.Type: ApplicationFiled: December 4, 2002Publication date: April 17, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hiroyuki Kouno, Toshio Kumamoto, Takahiro Miki, Hisayasu Satoh
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Patent number: 6538589Abstract: A digital &Dgr;&Sgr; modulator comprises a first-stage 1-bit &Dgr;&Sgr; modulator provided with an 1-bit (1 is an arbitrary natural number) quantizer, for modulating digital data, a correction logic for multiplying a quantization error caused in the 1-bit quantizer by a correction so that the quantization error caused in the 1-bit quantizer is eliminated at an output of the first-stage 1-bit &Dgr;&Sgr; modulator, and a next-stage m-bit &Dgr;&Sgr; modulator provided with an m-bit (m is an arbitrary natural number larger than 1) quantizer, for modulating and feeding the quantization error which is multiplied by the correction by the correction logic back to the first-stage 1-bit &Dgr;&Sgr; modulator.Type: GrantFiled: May 2, 2002Date of Patent: March 25, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takashi Okuda, Toshio Kumamoto, Yasuo Morimoto
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Patent number: 6522007Abstract: A gate electrode has a relatively long gate length of e.g., about 10 &mgr;m. In a region immediately above the gate electrode which is sandwiched between first-layer metals provided is a metal dummy pattern having a width in the first direction and extending in the second direction perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern in the second direction is equal to a geometric center of the gate electrode in the second direction. This maintains the symmetry in shape of the metal dummy pattern as viewed from the gate electrode. Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.Type: GrantFiled: October 12, 2001Date of Patent: February 18, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Hiroyuki Kouno, Toshio Kumamoto, Takahiro Miki, Hisayasu Satoh
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Publication number: 20030006922Abstract: When forming PDM pulses by a D/A converter in accordance with digital signals, the D/A converter causes at least one of the rising stage and the falling stage of each of the PDM pulses to change stepwise. In addition, when forming PWM pulses by another D/A converter, the D/A converter causes at least one of the rising stage and the falling stage of each of the PWM pulses to change stepwise.Type: ApplicationFiled: May 14, 2002Publication date: January 9, 2003Inventors: Yasuo Morimoto, Toshio Kumamoto, Takashi Okuda, Takahiro Miki
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Publication number: 20020196169Abstract: A digital &Dgr;&Sgr; modulator comprises a first-stage 1-bit &Dgr;&Sgr; modulator provided with an 1-bit (1 is an arbitrary natural number) quantizer, for modulating digital data, a correction logic for multiplying a quantization error caused in the 1-bit quantizer by a correction so that the quantization error caused in the 1-bit quantizer is eliminated at an output of the first-stage 1-bit &Dgr;&Sgr; modulator, and a next-stage m-bit &Dgr;&Sgr; modulator provided with an m-bit (m is an arbitrary natural number larger than 1) quantizer, for modulating and feeding the quantization error which is multiplied by the correction by the correction logic back to the first-stage 1-bit &Dgr;&Sgr; modulator.Type: ApplicationFiled: May 2, 2002Publication date: December 26, 2002Inventors: Takashi Okuda, Toshio Kumamoto, Yasuo Morimoto
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Publication number: 20020190382Abstract: A gate electrode (1) has a relatively long gate length (L) of e.g., about 10 &mgr;m. In a region immediately above the gate electrode (1) which is sandwiched between first-layer metals (1AL; 4, 5) provided is a metal dummy pattern (6) having a width (W:<L) in the first direction (D1) and extending in the second direction (D2) perpendicular to a direction of gate length (direction of current flow). Moreover, a geometric center of the metal dummy pattern (6) in the second direction (D2) is equal to a geometric center (GC) of the gate electrode (1) in the second direction (D2). This maintains the symmetry in shape of the metal dummy pattern (6) as viewed from the gate electrode (1). Such a structure can make deterioration in characteristics of a plurality of elements uniform while maintaining the essential effect of a metal CMP.Type: ApplicationFiled: October 12, 2001Publication date: December 19, 2002Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hiroyuki Kouno, Toshio Kumamoto, Takahiro Miki, Hisayasu Satoh
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Publication number: 20020123202Abstract: A semiconductor device of the invention has a plurality of resistor elements formed on an element isolating oxide film in predetermined regions on a surface of a semiconductor substrate. Active regions are furnished close to the resistor elements. This allows the element isolating oxide film near the resistor elements to be divided into suitable strips, forestalling a concave formation at the center of the element isolating oxide film upon polishing of the film by CMP and thereby enhancing dimensional accuracy of the resistor elements upon fabrication.Type: ApplicationFiled: September 24, 2001Publication date: September 5, 2002Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Hiroyuki Amishiro, Toshio Kumamoto, Motoshige Igarashi, Kenji Yamaguchi
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Patent number: 6323794Abstract: Modulators (M1 to Mk (k≧2)) are connected in a multi-stage such that each of quantization errors (e1, e2, . . . ) of the modulators (M1 to Mk−1) is fed to the input of the next stage modulator. Each output signal of the modulators (M2 to Mk) is fed back to the input of the immediately preceding modulator. The modulators (M1 to Mk) are all first-order modulators. Only the final stage modulator (Mk) has a multi-bit quantizer (6), and all the preceding modulators (M1 to Mk−1) have an 1-bit quantizer (3). Accordingly, a noise-shaping equal to that of a multi-bit higher-order modulator is realized on a small-scale circuit while retaining stability.Type: GrantFiled: November 10, 1999Date of Patent: November 27, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takashi Okuda, Toshio Kumamoto, Yasuo Morimoto