Patents by Inventor Toshio Ueda

Toshio Ueda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6104362
    Abstract: A panel display has a display panel including a plurality of cells to be selectively discharged to an address driver for setting the plurality of cells to states represented by display data. The panel display also has a display glowing driver for enabling the plurality of cells to glow according to the set states. One frame during which one screen is displayed has a plurality of sub-frames and glowing periods within the sub-frames, during which the display cells are enabled to glow by the display glowing driver. The said sub-frames are weighted in order to achieve gray-scale display. The display panel also has a display load calculating circuit for calculating a display load to be imposed on a whole display surface during each sub-frame. In addition, a corrected period calculating circuit calculates a corrected period of a glowing period, during which the display cells are enabled to glow by the display glowing driver according to display loads to be imposed during each sub-frame.
    Type: Grant
    Filed: July 21, 1999
    Date of Patent: August 15, 2000
    Assignee: Fujitsu Limited
    Inventors: Hirohito Kuriyama, Masaya Tajima, Toshio Ueda, Katsuhiro Ishida, Akira Yamamoto
  • Patent number: 6100859
    Abstract: A display panel has a plurality of cells to be selectively discharged to glow, an addressing unit for setting the plurality of cells to states represented by display data, and a display glowing unit for enabling the plurality of cells to glow according to set states. A display data quantity counter exists for each line that detects display data to be displayed line by line and counts the number of bits as a quantity of detected display data. A frequency of sustaining discharge is set line by line on the basis of the quantity of display data per line which is provided by the display data quantity counter.
    Type: Grant
    Filed: May 2, 1996
    Date of Patent: August 8, 2000
    Assignee: Fujitsu Limited
    Inventors: Hirohito Kuriyama, Masaya Tajima, Toshio Ueda, Katsuhiro Ishida, Akira Yamamoto
  • Patent number: 6069609
    Abstract: An image processing device has an error distribution unit, and a multiplier. The error distribution unit carries out an error distribution operation to artificially increase the number of shades to be displayed on a display. The multiplier multiplies an input signal by a multiplication coefficient, so that the input signal is separated into display data and error data along a bit boundary and the error distribution operation is carried out on the input signal. Further, a semiconductor integrated circuit has a dither pattern generator, an adder, and an error distribution unit. The dither pattern generator stores a plurality of dither patterns in advance and receives an input image signal, the adder receives the input image signal and a pattern signal from the dither pattern generator, and the error distribution unit carries out an error distribution operation on the output of the adder. Therefore, the image processing device can realize a smooth display characteristic for the entire range of input shades.
    Type: Grant
    Filed: February 28, 1996
    Date of Patent: May 30, 2000
    Assignee: Fujitsu Limited
    Inventors: Katsuhiro Ishida, Toshio Ueda, Masaya Tajima, Yukio Otobe, Masahiro Yoshida, Nobuaki Otaka
  • Patent number: 6052105
    Abstract: A wave generation circuit is disclosed, in which a complex waveform can be generated without increasing the ROM data amount or increasing the reading rate. Waveform data relating to a waveform and the generation thereof are stored in a ROM for each cycle. An address signal for reading the waveform data sequentially is produced sequentially by an address generation circuit. The waveform data read out are sequentially reproduced into a waveform signal by a waveform data output circuit. In a wave generating circuit including the ROM and the address generation circuit, the waveform data includes the extension information instructing to extend and reproduce the waveform data for a particular cycle.
    Type: Grant
    Filed: June 4, 1997
    Date of Patent: April 18, 2000
    Assignee: Fujitsu Limited
    Inventors: Akira Yamamoto, Masaya Tajima, Toshio Ueda, Hirohito Kuriyama, Katsuhiro Ishida, Yoshikazu Kanazawa
  • Patent number: 6023258
    Abstract: The present invention provides a flat display including a high-speed arithmetic logic facility so that, even when a data signal for a first line follows immediately after a frame start signal, the display displays an image with stable display quality quickly. For controlling driving signals in a flat display, each sub-frame of a temporally-segmented frame comprises at least an initialization period S1' during which a display screen is initialized, an addressing period S2 during which a plurality of cells are selected and written with display data, and a sustaining discharge period S3 during which the cells which contain display data are discharged so as to emit light for a given period of time. The flat display includes an initialization start time control unit 100 that detects the input of a display start signal V.sub.SYNC for one frame, and controls an initialization start time ST of the initialization period S1' so that the ST will precede an instant of input of a frame start signal V.sub.SYNC.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: February 8, 2000
    Assignee: Fujitsu Limited
    Inventors: Hirohito Kuriyama, Toshio Ueda, Keiichi Kaneko, Akira Yamamoto
  • Patent number: 6002381
    Abstract: A PDP not posing the problem that previous display data appears at the time of activation, and a wave generating circuit capable of generating a complex wave without the necessity of expanding a quantity of ROM data and of increasing a reading speed have been disclosed. A plasma display panel display comprising a plasma display panel that includes a plurality of cells to be selectively discharged to glow, a reset unit for bringing the plurality of cells to a given state, an addressing unit for setting the plurality of cells to states associated with display data, and a sustaining discharge unit for enabling the plurality of cells to glow according to the set states further comprises an operation halt factor detector for detecting the fact that a factor of halting the operation of the plasma display panel has occurred, and an initialization unit that when it is detected that the operation halt factor has occurred, initializes memory information in the plasma display panel.
    Type: Grant
    Filed: June 10, 1996
    Date of Patent: December 14, 1999
    Assignee: Fujitsu Limited
    Inventors: Shigetoshi Tomio, Yoshikazu Kanazawa, Tomokatsu Kishi, Tetsuya Sakamoto, Akira Yamamoto, Masaya Tajima, Toshio Ueda, Hirohito Kuriyama, Katsuhiro Ishida
  • Patent number: 5995203
    Abstract: When the scanning of a mask stage and a substrate stage is started, an interferometer measures the position of the substrate stage, while an interferometer unit differentiates the output of the interferometer to give a speed signal on the substrate stage, and delivers this speed signal. A main control unit produces a target value for the amount of exposure light adapted to this speed signal. A light amount adjustment system adjusts the amount of exposure light from an exposure light source in response to the target value calculated by the main control unit. Thus, exposure with appropriate amount of light adapted to the speed of the substrate stage is performed over all of the time zones from the start of drive of the substrate stage in the scan direction until its standstill. Hence, the exposure time can be shortened, and the throughput can be increased, in comparison with exposure being performed only in the constant speed zone of the stage.
    Type: Grant
    Filed: September 18, 1996
    Date of Patent: November 30, 1999
    Assignee: Nikon Corporation
    Inventor: Toshio Ueda
  • Patent number: 5973655
    Abstract: A flat display comprising an address current detecting means 3 for detecting a value of address current consumed for each frame to be displayed on the flat display, a comparator 4 for comparing the address current value detected by the address current detecting means 3 with a given reference value, and an address frequency control means 5 for controlling address frequencies related to a display frame in response to the output of the comparator 4.
    Type: Grant
    Filed: November 29, 1996
    Date of Patent: October 26, 1999
    Assignee: Fujitsu Limited
    Inventors: Takashi Fujisaki, Akira Otsuka, Toshio Ueda, Sigetoshi Tomio, Masaya Tajima
  • Patent number: 5943032
    Abstract: A method of controlling the gray scale of a plasma display device has a forming step of forming a frame for an image by a plurality of subframes each having a different brightness, a setting step of setting the number of sustain emissions of each subframe in an anti-geometrical progression corresponding to the brightness of each subframe, and a displaying step of displaying the image on the plasma display device by a gray scale display having a specific brightness. The number of sustain emissions in each subframe is set individually by the each subframe, and this establishes a linear relation between the gray level and the corresponding brightness Therefore, an enhancement of display quality of the plasma display device can be realized.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: August 24, 1999
    Assignee: Fujitsu Limited
    Inventors: Keishin Nagaoka, Masaya Tajima, Yoshimasa Awata, Yoshikazu Kanazawa, Toshio Ueda
  • Patent number: 5907316
    Abstract: A method displays a halftone image on a display unit by using a frame division technique that divides each frame of the halftone image into subframes each having a specific sustain discharge period to provide a specific intensity level. The method differs the position of the halftone image on the display unit from subframe to subframe in each frame. The method is capable of displaying dynamic halftone images without intensity level disturbance, smears, or false color contours.
    Type: Grant
    Filed: August 5, 1996
    Date of Patent: May 25, 1999
    Assignee: Fujitsu Limited
    Inventors: Shigeo Mikoshiba, Takahiro Yamaguchi, Kohsaku Toda, Tsutae Shinoda, Kyoji Kariya, Toshio Ueda, Katsuhiro Ishida
  • Patent number: 5818419
    Abstract: A display device, for displaying a multiple-level gray scale picture through a frame having a plurality of sub-frames which are time-divided in accordance with weight value of gray scale for each sub-frame, comprises sub-frame selection circuit, being supplied with an vertical synchronization signal, for selecting the number of the sub-frames which can be displayed within the period for the single frame in accordance with the frequency of the vertical synchronization signal, and for providing a sub-frame selection signal corresponding to the number of the sub-frames; and display control circuit, operatively connected to the sub-frame selection circuit, for receiving the sub-frame selection signal and an input display data signal and for controlling said display of the multi-level gray scale picture in accordance with the selected number of the sub-frames. When the frequency of Vsync.
    Type: Grant
    Filed: May 28, 1996
    Date of Patent: October 6, 1998
    Assignee: Fujitsu Limited
    Inventors: Masaya Tajima, Toshio Ueda, Hirohito Kuriyama, Katsuhiro Ishida, Akira Yamamoto
  • Patent number: 5745085
    Abstract: A flat panel display operates at a low level of power consumption without limiting a display rate and produces an image display of stable brightness, suppressing any change in brightness resultant from a change in the display rate or in a level of a display voltage, Vs. A turn on frequency control unit controls the turn on frequency of the display as a function of the frequency of discharge-sustaining voltage pulses, a current detecting unit detects a level of current flowing into the cell portions of the display panel, and a current converting value setting unit arbitrarily sets a converging value of the current that flows into the cell portions.
    Type: Grant
    Filed: March 28, 1995
    Date of Patent: April 28, 1998
    Assignee: Fujitsu Limited
    Inventors: Shigetoshi Tomio, Toshio Ueda
  • Patent number: 5699145
    Abstract: A scanning type exposure apparatus includes a mask stage which can move a mask along a predetermined scanning direction; a substrate stage which can move a substrate, onto which a pattern on the mask is to be transferred, along the scanning direction; a fine movement stage which is arranged on one of the mask stage and the substrate stage, and is movable along the scanning direction relative to the one stage; a first measuring device for detecting the position, along the scanning direction, of the fine movement stage; a second measuring device for detecting the position, along the scanning direction, of the other one of the mask stage and the substrate stage; a speed controller for controlling the ratio between the speeds of the mask stage and the substrate stage to a predetermined value while the pattern on the mask is scanning-exposed on the substrate; and a control device for controlling the position of the fine movement stage in accordance with the difference between the position measured by the first mea
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: December 16, 1997
    Assignee: Nikon Corporation
    Inventors: Susumu Makinouchi, Toshio Ueda
  • Patent number: 5663783
    Abstract: In a stage-drive controlling device used in a scanning projection exposure apparatus, a targeted speed Iwy is imparted to a speed control system for controlling the speed of a substrate stage, and a targeted speed Irc is concurrently imparted to a speed control system for controlling the speed of a mask stage such that the two stages assume a predetermined positional relationship. A deviation Xrc in the speed of the Speed control system is multiplied by 1/4 (multiplied by the magnification of projection) by a deviation feedback system, and the multiplied value is fed back as a targeted input to the speed control system. For this reason, the following formula holds: Ywy={Kwy/(s+Kwy)}.times.(Yrc/4). If the response of the speed control system side (substrate stage side) is good, even if the speed response of the speed control system side (mask stage side) is poor, the speed ratio between the two stages is kept at 4:1.
    Type: Grant
    Filed: March 25, 1996
    Date of Patent: September 2, 1997
    Assignee: Nikon Corporation
    Inventor: Toshio Ueda
  • Patent number: 5583527
    Abstract: In a flat display, an address current detecting unit detects a value of address current consumed during each display frame, a comparator compares the address current value detected by the address current detecting unit with a given reference value, and an address-frequency control unit controls address frequencies related to the display frame in response to the output of the comparator.
    Type: Grant
    Filed: January 31, 1994
    Date of Patent: December 10, 1996
    Assignee: Fujitsu Limited
    Inventors: Takashi Fujisaki, Akira Otsuka, Toshio Ueda, Sigetoshi Tomio, Masaya Tajima
  • Patent number: 5269855
    Abstract: A permanent magnet made of an R--Fe--B--C or R--Fe--Co--B--C based alloy, where R is at least one rare-earth element, comprising individual magnetic crystal grains that are covered with an oxidation-resistant protective film. The protective film surrounding the individual magnetic crystal grains having a thickness of 0.001-30 .mu.m and 0.05-16 wt. % of the protective film comprising C.
    Type: Grant
    Filed: February 27, 1992
    Date of Patent: December 14, 1993
    Assignee: Dowa Mining Co., Ltd.
    Inventors: Toshio Ueda, Yuichi Sato, Seiji Isoyama, Seiichi Hisano
  • Patent number: 5183630
    Abstract: A process for producing a permanent magnet alloy based on a R--Fe--B--C system wherein R is at least one of the rare earth elements including Y, comprising the steps of preparing a molten crude alloy, producing a powder directly therefrom or after casting it into an alloy ingot and then grinding it into the powder, compacting the thus obtained powder and sintering the compacted product, the ingot or powder of the alloy before being sent to the compacting step being subjected to a heat treatment which is carried out at a temperature of 500.degree.-1,100.degree. C. for a period of 0.5 hour or more so as to produce a permanent magnet alloy based on an a R--Fe--B--C system whose individual magnetic crystal grains are covered with an oxidation-resistant protective film which has a C content higher than that of the individual crystal grains.
    Type: Grant
    Filed: June 4, 1991
    Date of Patent: February 2, 1993
    Assignee: Dowa Mining Co., Ltd.
    Inventors: Toshio Ueda, Yuichi Sato, Masayasu Senda, Seiji Isoyama, Seiichi Hisano
  • Patent number: 5147473
    Abstract: A permanent magnet made of an R-Fe-B-C or R-Fe-Co-B-C based alloy (where R is at least one rare-earth element) consisting of its individual magnetic crystal grains that are covered with an oxidation-resistant protective film is promising as a practicable next-generation magnet because of its having not only excellent magnetic properties inclusive of magnetic force that surpasses Sm-Co based magnets but also such highly improved oxidation resistance that may withstand use in practical applications for a prolonged time period without being coated on its outermost exposed surface with an oxidation-resistant protective film. Said protective film surrounding the individual magnetic crystal grains contains at least one, preferably substantially all, of the alloying elements of which said magnetic crystal grains are made, with 0.05-16 wt. %, preferably 0.1-16 wt. % of said protective film being composed of C.
    Type: Grant
    Filed: August 9, 1990
    Date of Patent: September 15, 1992
    Assignee: Dowa Mining Co., Ltd.
    Inventors: Toshio Ueda, Yuichi Sato, Masayasu Senda, Seiji Isoyama, Seiichi Hisano
  • Patent number: 4812540
    Abstract: A monoallylamine-diallylamine derivative copolymer with a high degree of polymerization can be obtained in a high yield by using a radical initiator containing an azo group and a group having cationic nitrogen atom in the molecule.
    Type: Grant
    Filed: May 12, 1987
    Date of Patent: March 14, 1989
    Assignee: Nitto Boseki Co., Ltd.
    Inventors: Kenji Kageno, Toshio Ueda, Susumu Harada
  • Patent number: 4789494
    Abstract: There is disclosed in hydrothermal process for producing a magnetoplumbitic ferrite powder of the formula:MO.n(Fe.sub.2-x M'.sub.x O.sub.3) (1)wherein M is one or more metals selected from the group consisting of Ba, Sr, Ca and Pb; n is a number of 3 to 6; M' is at least one component selected from the group consisting of Si, Ta, Sb, Nb, Zr and Ti, or a combination of that component with at least one other component selected from the group consisting of Ni, Co, Cu, Mg, Mn and Zn; x is a number of 0.01 to 0.7, which process comprises carrying out the reaction of said ferrite powder formation in a H.sub.2 O medium at a temperature higher than 100.degree. C. and in the presence of an alkali having an alkali equivalent ratio greater than 1.0 with respect to an acid residue or in the presence of an alkali that provides the reaction system with a pH of 11 or more, said reaction being caused to proceed in the presence of "agent A" or in the present of both "agent A" and "agent B".
    Type: Grant
    Filed: January 9, 1987
    Date of Patent: December 6, 1988
    Assignee: Dowa Mining Co., Ltd.
    Inventors: Katsuo Aoki, Toshio Ueda