Patents by Inventor Toshitaka Fukushima

Toshitaka Fukushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190280348
    Abstract: A battery-type power supply device realizes data transmission while also supplying power to a battery-driven external load device in a state in which the battery-type power supply device is mounted in a battery box of the external load device. The battery-type power supply device is mountable in the battery box of the external load device, has a shape and dimensions conforming to battery standards, and is capable of housing a small-size battery therein. An output transistor is interposed between a housed battery and an outer electrode terminal, and opening and closing of the output transistor are controlled by a PWM control section at a duty ratio corresponding to an instruction received from an external information processing device by a radio communication section, so that the battery type power supply device thereby functions as a switching power supply.
    Type: Application
    Filed: May 29, 2019
    Publication date: September 12, 2019
    Inventors: Toshitaka FUKUSHIMA, Akihiro OKABE
  • Patent number: 9092015
    Abstract: There is provided an electronic timepiece that includes a solar panel which receives light to generate electric power, is operated with the electric power supplied from a secondary battery charged with output voltage of the solar panel, and includes a normal mode in which clock display is performed on a display unit and a power saving mode in which clock display on the display unit is stopped, based on illuminance detection of the solar panel, the electronic timepiece including: a mode control unit which switches cycles of the illuminance detection, by setting a cycle of the illuminance detection of the normal mode as a first cycle (for example, one minute), and a cycle of the illuminance detection of the power saving mode as a second cycle (for example, two seconds).
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: July 28, 2015
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Kazuo Kato, Akira Takakura, Tomohiro Ihashi, Takanori Hasegawa, Toshitaka Fukushima
  • Patent number: 9036455
    Abstract: An electronic timepiece is operated with a power-supply voltage from a secondary battery charged with a voltage from a solar panel. An oscillation circuit generates and supplies a clock signal to a CPU when the voltage charged to the battery is lower than a first voltage. A reset circuit resets the CPU when the voltage charged to the battery does not exceed a second voltage higher than the first voltage, and cancels the reset of the CPU when the voltage charged to the second battery exceeds the second voltage. The CPU starts an operation when the voltage charged to the secondary battery exceeds the second voltage and the reset is cancelled, and performs a time-of-day display on a display unit when the voltage charged to the secondary battery is equal to or higher than a third voltage higher than the second voltage.
    Type: Grant
    Filed: January 10, 2013
    Date of Patent: May 19, 2015
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Kazuo Kato, Akira Takakura, Tomohiro Ihashi, Takanori Hasegawa, Toshitaka Fukushima
  • Patent number: 8982675
    Abstract: A power supply unit has a first power supply circuit that supplies a voltage to a load driving unit and a second power supply circuit that supplies a voltage to circuits other than the load driving unit. A first switching unit connects any one of a power supply that supplies a power supply voltage and a voltage step-down circuit that supplies a step-down voltage of the power supply voltage to the first power supply circuit. A second switching unit connects any one of the power supply and the voltage step-down circuit to the second power supply circuit. A control unit controls the connection by the first switching unit and the connection by the second switching unit to switch the voltage supplied to the first power supply circuit and the voltage supplied to the second power supply circuit in accordance with properties of the load driving unit.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: March 17, 2015
    Assignee: Seiko Instruments Inc.
    Inventors: Kazuo Kato, Akira Takakura, Toshitaka Fukushima, Keisuke Tsubata, Hisao Nakamura, Tomohiro Ihashi, Yoshinori Sugai, Eriko Noguchi, Satoshi Sakai, Takanori Hasegawa
  • Publication number: 20130003508
    Abstract: An electronic apparatus includes a first frequency division portion that frequency-divides a clock signal by a first frequency division ratio, a second frequency division portion that frequency-divides the first clock signal which has been frequency-divided by the first frequency division portion by a second frequency division ratio, and a regulation frequency division portion that performs logical regulation of the clock signal using a second clock signal which has been frequency-divided by the second frequency division portion.
    Type: Application
    Filed: June 27, 2012
    Publication date: January 3, 2013
    Inventors: Kazuo KATO, Akira Takakura, Toshitaka Fukushima, Keisuke Tsubata, Hisao Nakamura, Tomohiro Ihashi, Yoshinori Sugai, Eriko Noguchi, Satoshi Sakai, Takanori Hasegawa
  • Publication number: 20120057437
    Abstract: A power supply unit includes: a first power supply circuit that supplies a voltage to a load driving unit that drives a load unit; a second power supply circuit that supplies a voltage to circuits other than the load driving unit; and a control unit that switches the voltage supplied to the first power supply circuit and the voltage supplied to the second power supply circuit in accordance with properties of the load driving unit.
    Type: Application
    Filed: August 31, 2011
    Publication date: March 8, 2012
    Inventors: Kazuo Kato, Akira Takakura, Toshitaka Fukushima, Keisuke Tsubata, Hisao Nakamura, Tomohiro Ihashi, Yoshinori Sugai, Eriko Noguchi, Satoshi Sakai, Takanori Hasegawa
  • Patent number: 5187720
    Abstract: The synchronous serial communication circuit transmits and receives data, which is added flag patterns for recognizing the coil winding direction at the first and last of data block, by the electromagnetic induction system using a pair of coils. So, the circuit provides modulation and demodulation circuits acting at the clock of twice of the transfer speed and a flag check circuit for recognizing the inversion of the coil winding direction by judging a state of the flag patterns included in the received data. The transmitted data is converted into the biphase signal by the modulation circuit and is transmitted by driving the coil using the biphase signal. The signal received by the coil is converted into the received data by the demodulation circuit. When the winding directions of coils does not agree, the flag check circuit recognizes the inversion of the coil winding direction and the received data is inverted by the demodulation circuit.
    Type: Grant
    Filed: December 17, 1990
    Date of Patent: February 16, 1993
    Assignee: Seiko Instruments Inc.
    Inventors: Koichi Shibata, Toshitaka Fukushima, Hiroyuki Watanabe, Shinichiro Miyahara, Osamu Imagawa
  • Patent number: 5187441
    Abstract: The portable information apparatus has a battery, a boosting circuit for boosting a voltage of the battery, a battery voltage detector for detecting a voltage level of the battery, an oscillating circuit for generating CPU clock and a counting circuit for counting the interval from the start of the oscillation of the CPU clock to the time when it becomes stable. The apparatus negates the output of the battery voltage detector during the interval counted by the counting circuit so that it can prevent the monitoring of the battery voltage lowering in the time of usual performance from influencing of the battery potential drop due to the transient current at the start of the performance of the boosting circuit and the oscillating circuit.
    Type: Grant
    Filed: December 11, 1990
    Date of Patent: February 16, 1993
    Assignee: Seiko Instruments Inc.
    Inventors: Koichi Shibata, Toshitaka Fukushima, Hiroyuki Watanabe, Shinichiro Miyahara, Osamu Imagawa
  • Patent number: 4943742
    Abstract: A semiconductor device used for, particularly, an output stage of a logic circuit is formed by a Schottky.barrier.diode clamping transistor. A clamping circuit is provided between a collector and a base for clamping a collector potential. The clamping circuit is formed by a Schottky.barrier.diode (SBD) and a series connected resistance coupled to the Schottky.barrier.diode. A collector resistance is divided by resistance division using the series resistance (FIG. 6).
    Type: Grant
    Filed: April 4, 1989
    Date of Patent: July 24, 1990
    Assignee: Fujitsu Limited
    Inventor: Toshitaka Fukushima
  • Patent number: 4922319
    Abstract: A field programmable device such as a PROM in which a memory cell is formed from a series connection of a capacitor and a diode or FET. Programming is performed by forming a short circuit in an insulation film of the capacitor due to electrical breakdown of the capacitor. The capacitor is formed of first and second semiconductor layers and an insulation film between the two layers. The instability of short circuits due to further oxidation of the insulation film is avoided by the above described structure. The memory stored in the device is stabilized, and the reliability of the device is increased. The insulation film of the capacitor is oxidized or nitrided by ion implantation of oxygen or nitrogen into the semiconductor substrate, or polycrystalline material.
    Type: Grant
    Filed: July 5, 1989
    Date of Patent: May 1, 1990
    Assignee: Fujitsu Limited
    Inventor: Toshitaka Fukushima
  • Patent number: 4907062
    Abstract: A device equivalent to a wafer-scale integrated device is achieved by employing multiple IC chips installed on a silicon wafer. For fabricating the device, conventional IC chips of necessary different types are prepared, having their aluminum-wired surfaces coated with a silicon nitride film. These IC chips are placed on a substrate made of silicon keeping the wired faces face up. The wafer may be provided with depressions in which the chips are placed for precise positioning. Upon these chips and the wafer, a silicon layer is grown by a PVD method. The grown silicon layer fills gaps between the IC chips and binds the chips to each other and to the wafer, forming a single piece of wafer. Excessively grown silicon which is taller than the chips is removed by mechano-chemical polishing until the silicon nitride surfaces are exposed. During this polishing process, the silicon nitride film protects the wired surfaces from mechanical and chemical damage.
    Type: Grant
    Filed: October 14, 1988
    Date of Patent: March 6, 1990
    Assignee: Fujitsu Limited
    Inventor: Toshitaka Fukushima
  • Patent number: 4866004
    Abstract: In manufacturing processes of an integrated circuit, isolation technology between adjacent active elements on a substrate plays an important role. Groove isolation filled with dielectric is known as an effective way of achieving a high integration density, however the prior art methods of forming the isolation groove have the problem of formation of BIRD'S HEAD or BIRD'S BEAK portions around the isolation region, which restricts the integration density and deteriorates a flatness of the substrate. The method of forming isolation groove according to the present invention discloses that the method comprising the steps of removing a silicon oxide layer on a specified region surrounding the isolation groove, and depositing a silicon nitride layer directly on the substrate and forming the groove self-aligned using the above silicon oxide layer removal process, eliminates the above mentioned problems achieving a higher density of integration, a flatness of the substrate and improvement of the integrated circuit.
    Type: Grant
    Filed: August 25, 1988
    Date of Patent: September 12, 1989
    Assignee: Fujitsu Limited
    Inventor: Toshitaka Fukushima
  • Patent number: 4862459
    Abstract: For testing unwritten-in field programmable memory cells, some specified written-in cells have been previously provided in the semiconductor device. In the first method, while a readout circuit, which reads datum written in the memory cell, is enabled, addressing-signals selecting the memory cell are switched from the written-in cell to a unwritten-in cell to be tested. Then, the voltage of the bit line operatively connected to the selected unwritten-in cell starts to rise gradually to that of the unwritten-in cell. The delay of this rising voltage, after the moment of the address-switching, is detected by the voltage level at a predetermined time, or by the time when this rising voltage reaches a predetermined threshold level. This delay corresponds to the degradation of the cell by leakage. In the second method, while the readout circuit is disabled, the addressing signals are switched from selecting written-in cell to selecting an unwritten-in cell to be tested, and then the readout circuit is enabled.
    Type: Grant
    Filed: September 8, 1986
    Date of Patent: August 29, 1989
    Assignee: Fujitsu Limited
    Inventor: Toshitaka Fukushima
  • Patent number: 4839854
    Abstract: A system for collection of data and entry of the data to a host computer has a portable, hand held, data collector for collecting data and a stationary data relay for receiving the data from the data collector and for transmitting the data to the host computer. The portable hand held data collector includes a case of a size and shape to be held by one hand during use, a keyboard for inputting the data, displaying for displaying the data, memory for storing the data and an interface for transmitting the data to external. The data relay includes a case shaped to set the portable data collector thereon, of first interface for receiving the data transmitted from the data collector and of said interface for comunicating bidirectionally to the host computer.
    Type: Grant
    Filed: September 12, 1986
    Date of Patent: June 13, 1989
    Assignee: Seiko Instruments & Electronics Ltd.
    Inventors: Yasuo Sakami, Shigetaka Okina, Junichi Tsubouchi, Shozo Izaki, Toshitaka Fukushima, Hiroyuki Watanabe, Masao Ishizaki
  • Patent number: 4808550
    Abstract: An isolation groove structure comprises a deep isolation groove having a cross section with substantially straight and parallel side wall portions and a generally V-shaped bottom portion, and a shallow isolation groove having a generally V-shaped cross section. The V-shaped bottom portion of the deep isolation groove and the shallow isolation groove being formed simultaneously by anisotropic etching.
    Type: Grant
    Filed: July 8, 1988
    Date of Patent: February 28, 1989
    Assignee: Fujitsu Limited
    Inventor: Toshitaka Fukushima
  • Patent number: 4805141
    Abstract: A semiconductor device having a vertical transistor consisting of a semiconductor substrate, a first semiconductor region, and a second semiconductor region operatively functioning as a collector, a base, and an emitter of a transistor. By providing a high concentration region in the first semiconductor region, the base width of the transistor is narrowed. In a PROM, a reverse current preventing transistor with such a narrowed base width in each memory cell can be driven by a decoder/driver with a lowered driving power consumption.
    Type: Grant
    Filed: November 12, 1986
    Date of Patent: February 14, 1989
    Assignee: Fujitsu Limited
    Inventor: Toshitaka Fukushima
  • Patent number: 4792833
    Abstract: In a junction-shorting type PROM, including transistors, a highly doped region having the same conductivity type as a base is provided between a pair of memory cells. This region is a base contact region which commonly connects paired bases at a surface terminal connected to a word line. The base contact region also extends into the substrate, which is a collector, and prevents minority carries in each of the paired bases from diffusing into an adjacent base, and thus, prevents influence between the paired memory cells. The base contact region may be isolated from emitter regions by a narrow groove filled with insulation material. The narrow groove is deeper than the emitter regions but shallower than the substrate. A memory cell block composed of the paired cells and the base contact region is isolated at its circumference by the narrow groove.
    Type: Grant
    Filed: November 24, 1986
    Date of Patent: December 20, 1988
    Assignee: Fujitsu Limited
    Inventor: Toshitaka Fukushima
  • Patent number: 4654688
    Abstract: A semiconductor device having a lateral transistor consisting of a semiconductor substrate, a first semiconductor region, and a second semiconductor region operatively functioning as a collector, a base, and an emitter of a transistor. By providing a high concentration region in the first semiconductor region, the base width of the transistor is narrowed. In a PROM, a reverse current preventing transistor with such a narrowed base width in each memory cell can be driven by a decoder/driver with a lowered driving power consumption.
    Type: Grant
    Filed: December 27, 1984
    Date of Patent: March 31, 1987
    Assignee: Fujitsu Limited
    Inventor: Toshitaka Fukushima
  • Patent number: 4635645
    Abstract: In an electronic sphygmomanometer for a vehicle having a Korotkoff sound detecting circuit, a cuff pressure detecting circuit, a Korotkoff reference signal generator, a central processing unit for receiving the output of the Korotkoff sound detecting circuit, the output of the cuff pressure detecting circuit and the output of the Korotkoff reference signal generating and determining a systolic and diastolic blood pressure and a display unit for indicating the systolic and diastolic blood pressure, the electronic sphygmomanometer includes a cardioelectric potential detecting circuit having one-shot pulse generating circuit and the Korotkoff reference signal generator includes a flip-flop for receiving a cardioelectric potential synchronizing signal and pulse pressure variations signal so that the electronic sphygmomanometer mounted on the vehicle is not very much adversely affected by the vibration and noise.
    Type: Grant
    Filed: March 2, 1984
    Date of Patent: January 13, 1987
    Assignee: Seiko Instruments & Electronics Ltd.
    Inventor: Toshitaka Fukushima
  • Patent number: 4617653
    Abstract: A semiconductor memory device includes a plurality of memory cells arranged in a matrix form and a decoder circuit selecting a row of the matrix in response to an address signal. The decoder circuit includes a first-stage decoder having a plurality of first-stage decoding elements and a second-stage decoder having a plurality of second-stage decoding elements. Each first-stage decoding element is connected to a plurality of second-stage decoding elements. Each of the first-stage decoding elements receives predetermined higher bits of the address signals. One of the first-stage decoding elements is selected upon one access command. Each of the plurality of second-stage decoding elements receives the address signals. One of the rows of the matrix is selected in response to the the address signals when the corresponding first-stage decoding element operates, whereby the power consumption is reduced.
    Type: Grant
    Filed: December 28, 1983
    Date of Patent: October 14, 1986
    Assignee: Fujitsu Limited
    Inventors: Yasuro Matsuzaki, Toshitaka Fukushima, Kouji Ueno